產品詳細資料

Rating Automotive Architecture Gate driver Control interface 3xPWM, 6xPWM Vs (min) (V) 4.5 Vs ABS (max) (V) 65 Features 1x low side current sense, Bootstrap Architecture for Gate Driver, HW based configuration, Supports 100% PWM Duty Cycle with Trickle Charge pump Operating temperature range (°C) -40 to 125
Rating Automotive Architecture Gate driver Control interface 3xPWM, 6xPWM Vs (min) (V) 4.5 Vs ABS (max) (V) 65 Features 1x low side current sense, Bootstrap Architecture for Gate Driver, HW based configuration, Supports 100% PWM Duty Cycle with Trickle Charge pump Operating temperature range (°C) -40 to 125
VQFN (RGF) 40 35 mm² 7 x 5
  • 65-V Three Phase Half-Bridge Gate Driver
    • Drives 3 High-Side and 3 Low-Side N-Channel MOSFETs (NMOS)
    • 4.5 to 60-V Operating Voltage Range
    • Supports 100% PWM Duty Cycle with Trickle Charge pump
  • Bootstrap based Gate Driver Architecture
    • 1000-mA Maximum Peak Source Current
    • 2000-mA Maximum Peak Sink Current
  • Integrated Current Sense Amplifier with low input offset (optimized for 1 shunt)
    • Adjustable Gain (5, 10, 20, 40 V/V)
  • Hardware interface provides simple configuration
  • Ultra-low power sleep mode <1 uA at 25 ̊C
  • 4-ns (typ) propagation delay matching between phases
  • Independent driver shutdown path (DRVOFF)
  • 65-V tolerant wake pin (nSLEEP)
  • Supports negative transients upto -10V on SHx
  • 6x and 3x PWM Modes
  • Supports 3.3-V, and 5-V Logic Inputs
  • Accurate LDO (AVDD), 3.3 V ±3%, 80 mA
  • Compact QFN Packages and Footprints
  • Adjustable VDS overcurrent threshold through VDSLVL pin
  • Adjustable deadtime through DT pin
  • Efficient System Design With Power Blocks
  • Integrated Protection Features
    • PVDD Undervoltage Lockout (PVDDUV)
    • GVDD Undervoltage (GVDDUV)
    • Bootstrap Undervoltage (BST_UV)
    • Overcurrent Protection (VDS_OCP, SEN_OCP)
    • Thermal Shutdown (OTSD)
    • Fault Condition Indicator (nFAULT)
  • 65-V Three Phase Half-Bridge Gate Driver
    • Drives 3 High-Side and 3 Low-Side N-Channel MOSFETs (NMOS)
    • 4.5 to 60-V Operating Voltage Range
    • Supports 100% PWM Duty Cycle with Trickle Charge pump
  • Bootstrap based Gate Driver Architecture
    • 1000-mA Maximum Peak Source Current
    • 2000-mA Maximum Peak Sink Current
  • Integrated Current Sense Amplifier with low input offset (optimized for 1 shunt)
    • Adjustable Gain (5, 10, 20, 40 V/V)
  • Hardware interface provides simple configuration
  • Ultra-low power sleep mode <1 uA at 25 ̊C
  • 4-ns (typ) propagation delay matching between phases
  • Independent driver shutdown path (DRVOFF)
  • 65-V tolerant wake pin (nSLEEP)
  • Supports negative transients upto -10V on SHx
  • 6x and 3x PWM Modes
  • Supports 3.3-V, and 5-V Logic Inputs
  • Accurate LDO (AVDD), 3.3 V ±3%, 80 mA
  • Compact QFN Packages and Footprints
  • Adjustable VDS overcurrent threshold through VDSLVL pin
  • Adjustable deadtime through DT pin
  • Efficient System Design With Power Blocks
  • Integrated Protection Features
    • PVDD Undervoltage Lockout (PVDDUV)
    • GVDD Undervoltage (GVDDUV)
    • Bootstrap Undervoltage (BST_UV)
    • Overcurrent Protection (VDS_OCP, SEN_OCP)
    • Thermal Shutdown (OTSD)
    • Fault Condition Indicator (nFAULT)

The DRV8329-Q1 family of devices is an integrated gate driver for three-phase applications. The devices provide three half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The device generates the correct gate drive voltages using an internal charge pump and enhances the high-side MOSFETs using a bootstrap circuit. A trickle charge pump is included to support 100% duty cycle. The Gate Drive architecture supports peak gate drive currents up to 1-A source and 2-A sink. The DRV8329-Q1 can operate from a single power supply and supports a wide input supply range of 4.5 to 60 V.

The 6x and 3x PWM modes allow for simple interfacing to controller circuits. The device has integrated accurate 3.3-V LDO that can be used to power external controller and can be used as reference for CSA. The configuration settings for the device are configurable through hardware (H/W) pins.

The DRV8329-Q1 devices integrate low-side current sense amplifier that allow current sensing for sum of current from all three phases of the drive stage.

A low-power sleep mode is provided to achieve low quiescent current by shutting down most of the internal circuitry. Internal protection functions are provided for undervoltage lockout, GVDD fault, MOSFET overcurrent, MOSFET short circuit, and overtemperature. Fault conditions are indicated on nFAULT pin.

The DRV8329-Q1 family of devices is an integrated gate driver for three-phase applications. The devices provide three half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The device generates the correct gate drive voltages using an internal charge pump and enhances the high-side MOSFETs using a bootstrap circuit. A trickle charge pump is included to support 100% duty cycle. The Gate Drive architecture supports peak gate drive currents up to 1-A source and 2-A sink. The DRV8329-Q1 can operate from a single power supply and supports a wide input supply range of 4.5 to 60 V.

The 6x and 3x PWM modes allow for simple interfacing to controller circuits. The device has integrated accurate 3.3-V LDO that can be used to power external controller and can be used as reference for CSA. The configuration settings for the device are configurable through hardware (H/W) pins.

The DRV8329-Q1 devices integrate low-side current sense amplifier that allow current sensing for sum of current from all three phases of the drive stage.

A low-power sleep mode is provided to achieve low quiescent current by shutting down most of the internal circuitry. Internal protection functions are provided for undervoltage lockout, GVDD fault, MOSFET overcurrent, MOSFET short circuit, and overtemperature. Fault conditions are indicated on nFAULT pin.

下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 1
類型 標題 日期
* Data sheet DRV8329-Q1 4.5 to 60 V Three-phase BLDC Gate Driver datasheet PDF | HTML 2023年 3月 7日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

DRV8329AEVM — 適用於三相 BLDC 閘極驅動器的 DRV8329A 評估模組

DRV8329AEVM 是以 BLDC 馬達 DRV8329A 閘極驅動器為基礎的 30-A、3 相無刷 DC 驅動級。DRV8329 包含三個二極體以供靴帶運作,無需使用外部二極體。此產品包含用於低壓側電流量測的電流分流放大器、80-mA 低壓差線性穩壓器、失效時間控制針腳、VDS 過電流位準針腳,以及閘極驅動器關閉針腳。EVM 包含開關、電位計和電阻器,可評估這些設定,以及 DRV8329 產品 A 變體 (6x PWM) 和 B 變體 (3x PWM) 的可配置性。

可向 EVM 提供最高 60 V 電壓,DRV8329 整合式低壓差線性穩壓器則可產生靴帶式 GVDD (...)

使用指南: PDF | HTML
TI.com 無法提供
封裝 引腳 下載
VQFN (RGF) 40 檢視選項

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 資格摘要
  • 進行中可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片