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LMH6521

現行

高性能雙 DVGA

立即訂購
產品規格表

LMH6521

現行
產品規格表 立即訂購

產品詳細資料

2nd harmonic (dBc) -84 3rd harmonic (dBc) 83 Frequency of harmonic distortion measurement (MHz) 200 Acl, min spec gain (V/V) 0.53 Architecture Fully Differential ADC Driver, VGA BW at Acl (MHz) 1400 Gain (max) (dB) 26 Gain (min) (dB) -5.5 Step size (dB) 0.5 Type RF VGA Iq per channel (typ) (mA) 113 Number of channels 2 Rating Catalog Operating temperature range (°C) -40 to 85 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.25 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 4.75 Vs (min) (V) 4.75 Vs (max) (V) 5.25
2nd harmonic (dBc) -84 3rd harmonic (dBc) 83 Frequency of harmonic distortion measurement (MHz) 200 Acl, min spec gain (V/V) 0.53 Architecture Fully Differential ADC Driver, VGA BW at Acl (MHz) 1400 Gain (max) (dB) 26 Gain (min) (dB) -5.5 Step size (dB) 0.5 Type RF VGA Iq per channel (typ) (mA) 113 Number of channels 2 Rating Catalog Operating temperature range (°C) -40 to 85 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.25 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 4.75 Vs (min) (V) 4.75 Vs (max) (V) 5.25
WQFN (RTV) 32 25 mm² 5 x 5
  • OIP3 of 48.5 dBm at 200 MHz
  • Maximum Voltage Gain of 26 dB
  • Gain Range: 31.5 dB with 0.5-dB Step Size
  • Channel Gain Matching of ±0.04 dB
  • Noise Figure: 7.3 dB at Maximum Gain
  • –3-dB Bandwidth of 1200 MHz
  • Low Power Dissipation
  • Independent Channel Power Down
  • Three Gain Control Modes:
    • Parallel Interface
    • Serial Interface (SPI)
    • Pulse Mode Interface
  • Temperature Range: –40°C to +85°C
  • Thermally-Enhanced, 32-Pin WQFN Package
  • OIP3 of 48.5 dBm at 200 MHz
  • Maximum Voltage Gain of 26 dB
  • Gain Range: 31.5 dB with 0.5-dB Step Size
  • Channel Gain Matching of ±0.04 dB
  • Noise Figure: 7.3 dB at Maximum Gain
  • –3-dB Bandwidth of 1200 MHz
  • Low Power Dissipation
  • Independent Channel Power Down
  • Three Gain Control Modes:
    • Parallel Interface
    • Serial Interface (SPI)
    • Pulse Mode Interface
  • Temperature Range: –40°C to +85°C
  • Thermally-Enhanced, 32-Pin WQFN Package

The LMH6521 contains two high performance, digitally controlled variable gain amplifiers (DVGA).

Both channels of the LMH6521 have an independent, digitally controlled attenuator followed by a high linearity, differential output amplifier. Each block has been optimized for low distortion and maximum system design flexibility. Each channel has a high speed power down mode.

The internal digitally controlled attenuator provides precise 0.5-dB gain steps over a 31.5-dB range. Serial and parallel programming options are provided. Serial mode programming uses the SPI interface. A pulse mode is also offered where simple up or down commands can change the gain one step at a time.

The output amplifier has a differential output allowing 10-VPPD signal swings on a single 5-V supply. The low impedance output provides maximum flexibility when driving filters or analog to digital converters.

The LMH6521 contains two high performance, digitally controlled variable gain amplifiers (DVGA).

Both channels of the LMH6521 have an independent, digitally controlled attenuator followed by a high linearity, differential output amplifier. Each block has been optimized for low distortion and maximum system design flexibility. Each channel has a high speed power down mode.

The internal digitally controlled attenuator provides precise 0.5-dB gain steps over a 31.5-dB range. Serial and parallel programming options are provided. Serial mode programming uses the SPI interface. A pulse mode is also offered where simple up or down commands can change the gain one step at a time.

The output amplifier has a differential output allowing 10-VPPD signal swings on a single 5-V supply. The low impedance output provides maximum flexibility when driving filters or analog to digital converters.
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類型 標題 日期
* Data sheet LMH6521 High Performance Dual DVGA datasheet (Rev. E) PDF | HTML 2016年 8月 23日
E-book The Signal e-book: A compendium of blog posts on op amp design topics 2017年 3月 28日
User guide Using the LMH6521 in DC Coupled Applications Design Guide 2015年 1月 8日
Design guide TSW1265 Dual-Wideband RF-to-Digital Receiver Design Guide 2013年 9月 3日
Design guide TSW1266 Wideband RF-to-Digital Complex Receiver-Feedback Signal Chain 2013年 9月 3日
Application note AN-1719 Noise Figure Analysis Fully Differential Amplifier (Rev. A) 2013年 5月 1日
EVM User's guide AN-2045 LMH6521EVAL Evaluation Board (Rev. A) 2013年 5月 1日
Application note AN-2235 Ckt Brd Design for LMH6517/21/22 & Other H-Sp IF/RF F Amp (Rev. A) 2013年 5月 1日
Application note Between the Amplifier and ADC: Managing Filter Loss in Communications Systems (Rev. B) 2013年 4月 26日
Application note Drivng HSpeed ADCs w/LMH6521 DVGA for High IF AC-Coupled Apps (Rev. A) 2013年 4月 26日
Application note Using High Speed Diff Amp to Drive ADCs (Rev. A) 2013年 4月 26日
More literature Featured High Speed Differential Amplifiers 2012年 10月 23日
Application note A Walk Along the Signal Path (High-Speed Signal Path) 2005年 3月 30日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

TSW1265EVM — 寬頻雙路接收器參考設計和評估平台

The TSW1265EVM is a wideband dual receiver reference design and evaluation platform. The signal chain allows conversion from RF to bits using a dual-channel downconverter mixer, the LMH6521 dual-channel DVGA, and the ADS4249 14-bit 250-MSPS ADC. The TSW1265EVM also includes the LMK04800 dual-PLL (...)

使用指南: PDF
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模擬型號

LMH6521 ADS2009 Spice Model

SNOJ009.ZIP (46 KB) - Spice Model
下載
模擬型號

LMH6521 PSpice Model

SNOM715.ZIP (68 KB) - PSpice Model
下載
模擬型號

LMH6521 TINA-TI Reference Design

SNOM321.TSC (286 KB) - TINA-TI Reference Design
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模擬型號

LMH6521 TINA-TI Spice Model

SNOM322.ZIP (8 KB) - TINA-TI Spice Model
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參考設計

TIDA-00360 — 具 16 位元 ADC 和 100 MHz IF 頻寬的 700–2700 MHz 雙通道接收器參考設計

The increasing demand on wireless networks to provide faster data links to customers has driven transceiver hardware to increasingly demanding performance with enough bandwidth to support the largest standardized multi-carrier frequency bands (with band aggregation in some cases) and enough (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00353 — JESD204B 串列鏈路的均衡最佳化參考設計

Employing equalization techniques is an effective way of compensating for channel loss in JESD204B high speed serial interfaces for data converters. This reference design features the ADC16DX370, a dual 16-bit, 370 MSPS analog-to-digital converter (ADC) that utilizes de-emphasis equalization to (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00074 — 寬頻射頻轉數位複雜接收器 - 回饋訊號鏈

This is a wideband complex-receiver reference design and evaluation platform that is ideally suited for use as a feedback receiver for transmitter digital predistortion. The EVM signal chain is ideal for high intermediate-frequency (IF) complex-feedback applications and contains a complex (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00073 — 雙寬頻射頻轉數位接收器設計

The TSW1265EVM is an example design of a wideband RF to digital dual receiver solution capable of digitizing up to 125MHz of spectrum. The system provides a reference on how to use the ADS4249, LMH6521, LMK0480x, and a dual mixer to achieve this.  This reference EVEM coupled with a capture (...)
Design guide: PDF
電路圖: PDF
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