LMK00105
- 5 LVCMOS Outputs, DC to 200 MHz
- Universal Input
- LVPECL
- LVDS
- HCSL
- SSTL
- LVCMOS and LVTTL
- Crystal Oscillator Interface
- Crystal Input Frequency: 10 to 40 MHz
- Output Skew: 6 ps
- Additive Phase Jitter
- 30 fs at 156.25 MHz (12 kHz to 20 MHz)
- Low Propagation Delay
- Operates With 3.3 or 2.5-V Core Supply Voltage
- Adjustable Output Power Supply
- 1.5 V, 1.8 V, 2.5 V, and 3.3 V for Each Bank
- 24-Pin WQFN Package (4.0 mm × 4.0 mm ×
0.8 mm)
The LMK00105 is a high-performance, low-noise LVCMOS fanout buffer which can distribute five ultra-low jitter clocks from a differential, single-ended, or crystal input. The LMK00105 supports synchronous output enable for glitch-free operation. The ultra low-skew, low-jitter, and high PSRR make this buffer ideally suited for various networking, telecom, server and storage area networking, RRU LO reference distribution, medical and test equipment applications.
The core voltage can be set to 2.5 or 3.3 V, while the output voltage can be set to 1.5, 1.8, 2.5 or 3.3 V. The LMK00105 can be easily configured through pin programming.
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技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | LMK00105 Ultra-Low Jitter LVCMOS Fanout Buffer and Level Translator With Universal Input datasheet (Rev. G) | PDF | HTML | 2014年 12月 16日 |
User guide | LMK00105 User’s Guide (Rev. A) | 2019年 7月 1日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
LMK00105BEVAL — 具有通用輸入的 LMK00105 超低抖動 LVCMOS 扇出緩沖器/位準轉換器
The LMK00105 Evaluation Board simplifies evaluation of the LMK00105 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input. Configuring and controlling the board is accomplished using on board switches.
CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
WQFN (RTW) | 24 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。