LP2998
- AEC-Q100 Test Guidance with the following results
(SO PowerPAD-8):- Device HBM ESD Classification Level H1C
- Junction Temperature Range –40°C to 125°C
- 1.35 V Minimum VDDQ
- Source and Sink Current
- Low Output Voltage Offset
- No External Resistors Required
- Linear Topology
- Suspend to Ram (STR) Functionality
- Low External Component Count
- Thermal Shutdown
The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR2 memory. The device also supports DDR3 and DDR3L VTT bus termination with VDDQ min of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5 A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2998 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.
An additional feature found on the LP2998 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | LP2998/LP2998-Q1 DDR Termination Regulator datasheet (Rev. K) | PDF | HTML | 2014年 8月 20日 |
| Application note | DDR VTT Power Solutions: A Competitive Analysis (Rev. A) | 2020年 7月 9日 | ||
| Application note | Limiting DDR Termination Regulators’ Inrush Current | 2016年 8月 23日 | ||
| Application note | AN-1254 DDR-SDRAM Termination Simplified Using a Linear Regulator (Rev. A) | 2013年 5月 6日 | ||
| Application note | Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs | 2010年 4月 28日 | ||
| Application note | Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices | 2010年 4月 20日 | ||
| Application note | Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472) | 2010年 3月 31日 | ||
| Application note | 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) | 2010年 3月 26日 | ||
| Application note | Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs | 2010年 3月 26日 | ||
| Application note | TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers | 2010年 3月 26日 |
設計與開發
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LP2998EVAL — 適用於 LP2998 的評估板
The LP2998 evaluation board is designed to provide the design Engineer with a fully functional prototype system in which to evaluate the LP2998 in both a static environment and with a complete memory system.
TIDA-010011 — 用於保護繼電器處理器模組的高效電源供應架構參考設計
PMP10630 — Xilinx Kintex UltraScale XCKU040 FPGA 電源解決方案、6W 參考設計
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| HSOIC (DDA) | 8 | Ultra Librarian |
| SOIC (D) | 8 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。