TPD2E2U06
- IEC 61000-4-2 Level 4
- ±25 kV (Contact discharge)
- ±30 kV (Air-gap discharge)
- IEC 61000-4-5 Surge protection
- 5.5-A Peak pulse current (8/20 µs Pulse)
- IO Capacitance 1.5 pF (Typ)
- DC Breakdown voltage 6.5 V (Min)
- Ultra-Low leakage current 10 nA (Max)
- Low ESD clamping voltage
- Industrial temperature range: –40°C to +125°C
- Small easy-to-route DRL and DCK package
The TPD2E2U06 is a dual-channel low capacitance TVS diode ESD protection device. The device offers ±25-kV contact and ±30-kV air-gap ESD protection in accordance with the IEC 61000-4-2 standard. The 1.5-pF line capacitance of the TPD2E2U06 makes the device suitable for a wide range of applications. Typical application interfaces are USB 2.0, LVDS, and I2C™.
技術文件
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檢視所有 8 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | TPD2E2U06 Dual-Channel High-Speed ESD Protection Device datasheet (Rev. C) | PDF | HTML | 2019年 12月 3日 |
| User guide | Reading and Understanding an ESD Protection Data Sheet (Rev. A) | PDF | HTML | 2023年 9月 19日 | |
| Product overview | Isolating I2C Signals (Rev. A) | PDF | HTML | 2023年 9月 1日 | |
| Selection guide | System-Level ESD Protection Guide (Rev. D) | 2022年 9月 7日 | ||
| Application note | ESD Packaging and Layout Guide (Rev. B) | PDF | HTML | 2022年 8月 18日 | |
| Selection guide | ESD by Interface Selection Guide (Rev. A) | 2017年 6月 26日 | ||
| White paper | Designing USB for short-to-battery tolerance in automotive environments | 2016年 2月 10日 | ||
| Analog Design Journal | Design Considerations for System-Level ESD Circuit Protection | 2012年 9月 25日 |
設計與開發
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開發板
ESDEVM — 通用 ESD 評估模組
<p>The electrostatic-sensitive device (ESD) evaluation module (EVM) is a development platform for most of our ESD portfolio. The board comes with all traditional ESD footprints in order to test any number of devices. Devices can be soldered onto their respect footprint and then tested.</p>
(...)
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
| 封裝 | 引腳 | 下載 |
|---|---|---|
| SOT-5X3 (DRL) | 5 | 檢視選項 |
| SOT-SC70 (DCK) | 3 | 檢視選項 |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。