UC1707
- Two independent Drivers
- 1.5A Totem Pole Outputs
- Inverting and Non-Inverting Inputs
- 40 ns Rise and Fall into 1000 pF
- High-Speed, Power MOSFET Compatible
- Low Cross-Conduction Current Spike
- Analog Shutdown with Optional Latch
- Low Quiescent Current
- 5 V to 40 V Operation
- Thermal Shutdown Protection
- 16-Pin Dual-In-Line Package
- 20-Pin PLCC and CLCC Package
The UC1707 family of power drivers is made with a high-speed Schottky process to interface between low-level control functions and high-power switching devices - particularly power MOSFETs. These devices contain two independent channels, each of which can be activated by either a high or low input logic level signal. Each output can source or sink up to 1.5 A as long as power dissipation limits are not exceeded.
Although each output can be activated independently with its own inputs, it can be forced low in common through the action either of a digital high signal at the Shutdown terminal or a differential low-level analog signal. The Shutdown command from either source can either be latching or not, depending on the status of the Latch Disable pin.
Supply voltage for both VIN and VC can independently range from 5 V to 40 V.
These devices are available in two-watt plastic "bat-wing" DIP for operation over a 0°C to 70°C temperature range and, with reduced power, in a hermetically sealed cerdip for 55°C to +125°C operation. Also available in surface mount DW, Q, L packages.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | Dual Channel Power Driver datasheet (Rev. B) | 2008年 9月 16日 | |
| Application brief | External Gate Resistor Selection Guide (Rev. A) | 2020年 2月 28日 | ||
| Application brief | Understanding Peak IOH and IOL Currents (Rev. A) | 2020年 2月 28日 | ||
| Application note | U-111, Practical Considerations in Current Mode Power Supplies | 1999年 9月 5日 | ||
| Application note | U-118 New Driver ICs Optimize High-Speed Power MOSFET Switching Characteristics | 1999年 9月 5日 | ||
| Application note | U-137 Practical Considerations in High Performance MOSFET, IGBT and MCT Gate | 1999年 9月 5日 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| CDIP (J) | 16 | Ultra Librarian |
| LCCC (FK) | 20 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點