
AFE7444IABJ ACTIVE
Quad-channel RF-sampling AFE with 14-bit 9-GSPS DAC and 3-GSPS ADC without bypass mode
Quality information
RoHS | Yes |
---|---|
REACH | Yes |
Lead finish / Ball material | SNAGCU |
MSL rating / Peak reflow | Level-3-260C-168 HR |
Quality, reliability & packaging information Information included:
|
View or download |
More AFE7444 information
Packaging information
Package | Pins | Package qty | Carrier: | Operating temperature range (°C) |
---|---|---|
FCBGA (ABJ) | 400 |
90 | JEDEC TRAY (5+1)
|
-40 to 85 |
Package | Pins | FCBGA (ABJ) | 400 |
---|---|
Package qty | Carrier: |
90 | JEDEC TRAY (5+1)
|
Operating temperature range (°C) | -40 to 85 |
Features for the AFE7444
- Four, 14-bit, 9-GSPS DACs
- Up to800-MHz signal bandwidth
- 1 DSA per channel tunes outputpower
- Four, 14-Bit, 3-GSPS ADCs
- Up to 800-MHzsignal bandwidth
- NSD: –151 dBFS/Hz
- AC performance atfIN = 2.6 GHz, –3 dBFS
- SNR: 55 dBFS
- SFDR: 73 dBc HD2 and HD3
- SFDR: 91 dBc worst spur
- 2 DSA per channel extends dynamicrange
- RF and digital powerdetectors
- RF frequency range: 10 MHz to 6 GHz
- Fast frequency hopping < 1 µs
- Receive digital signal path:
- dual DDC per ADC
- 3-phase coherent 32-bit NCOs perDDC
- Decimation ratio: 3x to32x
- Transmit digital signal path:
- DualDUC per DAC with 32-bit NCOs
- Interpolation ratio: 8x to 36x
- Sin(x)/xcorrection and configurable delay
- Power amplifier protection(PAP)
- JESD204B interface:
- 8transceivers at up to 15 Gbps
- Subclass 1 multichipsynchronization
- Clocks:
- InternalPLL and VCO with bypass option
- Clock output up to 3 GHz with clockdivider
- DAC power dissipation: 1.7 W/ch at 9 GSPS
- ADC power dissipation: 1.8 W/ch at 3 GSPS
- Package: 17-mm x 17-mm FC BGA, 0.8-mm pitch
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Description for the AFE7444
The AFE7444 is a quad-channel, wideband, RF-sampling analog front end (AFE) based on 14-bit,9-GSPS DACs and 14-bit, 3-GSPS ADCs. With operation at an RF of up to 6 GHz, this device enablesdirect RF sampling into the C-band frequency range without the need for additional frequencyconversions stages. This improvement in density and flexibility enables high-channel-count,multimission systems.
The DAC signal paths support interpolation and digital up conversion options that deliverup to 800 MHz of signal bandwidth. Thedifferential output path includes a digital step attenuator (DSA), which enables tuning of outputpower.
Each ADC input path includes a dual DSA and RF and Digital power detectors.Flexible decimation options provide optimization of data bandwidth.
An 8-lane (8 TX + 8 RX) subclass-1 compliant JESD204B interface operates at up to 15Gbps. A bypassable on-chip PLL simplifies clock operation with an optional clock output.
Pricing
Qty | Price (USD) |
---|---|
1+ | 1539.912 |