text.skipToContent text.skipToNavigation

CD74HC4094M96G3 ACTIVE

High Speed CMOS Logic 8-Stage Shift-and-Store Bus Register with 3-Stage Outputs

NEW - Custom reel may be available
Inventory: 2,500
 
Download data sheet for the CD74HC4094
  |   View additional information for the CD74HC4094

Quality information

RoHS Yes
REACH Yes
Lead finish / Ball material SN
MSL rating / Peak reflow Level-1-260C-UNLIM
Material content View
DPPM / MTBF / Fit rate View
Qualification summary View
Ongoing reliability monitoring View
Device marking View

Packaging information

Package | Pins Operating temperature range (°C) Package qty | Carrier:
SOIC (D) | 16 M (-55 to 125) 2,500 | LARGE T&R
Custom reel may be available
View more packaging information

Features for the  CD74HC4094

  • Buffered Inputs
  • Separate Serial Outputs Synchronous to Both
    Positive and Negative Clock Edges For Cascading
  • Fanout (Over Temperature Range)
    • Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . .–55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL
    Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC
      at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility,
      VIL= 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH

Description for the CD74HC4094

The ’HC4094and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input to parallel buffered three-stateoutputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the Output-Enable signal is high.

Two serial outputs are available for cascading a number of these devices. Data is available at the QS1 serial output terminal on positive clock edges to allow for high-speed operation in cascaded system in which the clock rise time is fast. The same serial information, available at the QS2 terminal on the next negative clock edge, provides a means for cascading these devices when the clock rise time is slow.

Pricing

Qty Price(USD)
1-99 $0.342
100-249 $0.232
250-999 $0.179
1,000+ $0.119