text.skipToContent text.skipToNavigation

SN74HC166DRG4 ACTIVE

8-Bit Parallel-Load Shift Registers

Same as: SN74HC166DRE4   This part number is identical to the part number listed above. You can only order quantities of the part number listed above.

NEW - Custom reel may be available
Inventory: 3,860  
 

Quality information

RoHS Yes
REACH Yes
Lead finish / Ball material NIPDAU
MSL rating / Peak reflow Level-1-260C-UNLIM
Quality, reliability
& packaging information

Information included:

  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
View or download

Packaging information

Package | Pins Package qty | Carrier: Operating temperature range (℃)
SOIC (D) | 16 2,500 | LARGE T&R
Custom reel may be available
-40 to 85
Package | Pins SOIC (D) | 16
Package qty | Carrier: 2,500 | LARGE T&R
Custom reel may be available
Operating temperature range (℃) -40 to 85
View TI packaging information

Features for the SN74HC166

  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 13 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Synchronous Load
  • Direct Overriding Clear
  • Parallel-to-Serial Conversion

Description for the SN74HC166

These parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding clear (CLR)\ input. The parallel-in or serial-in modes are established by the shift/load (SH/LD)\ input. When high, SH/LD\ enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high. CLR\ overrides all other inputs, including CLK, and resets all flip-flops to zero.

Pricing


Qty Price (USD)
1-99 0.296
100-249 0.201
250-999 0.155
1,000+ 0.103