Packaging information
| Package | Pins TSSOP (PW) | 16 |
| Operating temperature range (°C) -40 to 125 |
| Package qty | Carrier 2,000 | LARGE T&R |
Features for the SN74LV595A-Q1
- Qualified for automotive applications
- Available in wettable flank QFN (WBQB) package
- Customer-specific configuration control can be supported along with major-change approval
- 2-V to 5.5-V V CC operation
- Typical V OLP (output ground bounce) < 0.8 V at V CC = 3.3 V, T A = 25°C
- Typical V OHV (output V OH undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
- Supports mixed-mode voltage operation on all ports
- 8-bit serial-in, parallel-out shift
- I off supports partial-power-down mode operation
- Shift register has direct clear
Description for the SN74LV595A-Q1
The SN74LV595A-Q1 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear ( SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except Q H’ are in the high-impedance state.
The device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.