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Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers TIDA-01021 (ACTIVE)
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Key Document
- Multichannel JESD204B 15-GHz Clocking Reference Design (Rev. A)
(PDF 2105 KB)
14 Jun 2017
- TIDA-01021 Schematic and Block Diagram (Rev. A)
(PDF 1786 KB)
04 Jan 2018
Description
High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 wideband PLL with integrated VCOs to generate a 10 MHz to 15 GHz clock and SYSREF for JESD204B interfaces. The 10 KHz offset phase noise is < -104 dBc/Hz for a 15 GHz clock frequency. By using TI’s ADC12DJ3200 high speed converter EVMs, a board-to-board clock skew of <10ps is achieved and a SNR of 49.6 dB with a 5.25 GHz input signal. All key design theories are described, guiding users through the part selection process and design optimization. Finally, schematic, board layout, hardware testing, and results are also presented.
Features
- Up to 15GHz sample clock generation
- Multi-channel JESD204B compliant clock solution
- Low phase noise clocking for RF sampling ADC/DAC
- Configurable phase synchronization to achieve low skew in multi-channel system
- Supports TI’s high-speed converter and capture cards (ADC12DJ3200EVM, TSW14J56 / TSW14J57)
See the Important Notice and Disclaimer covering reference designs and other TI resources.
