TIDA-01021

Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers

TIDA-01021

Design files

Overview

High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 wideband PLL with integrated VCOs to generate a 10 MHz to 15 GHz clock and SYSREF for JESD204B interfaces. The 10 KHz offset phase noise is < -104 dBc/Hz for a 15 GHz clock frequency.  By using TI’s ADC12DJ3200 high speed converter EVMs, a board-to-board clock skew of <10ps is achieved and a SNR of 49.6 dB with a 5.25 GHz input signal. All key design theories are described, guiding users through the part selection process and design optimization.  Finally, schematic, board layout, hardware testing, and results are also presented.

Features
  • Up to 15GHz sample clock generation
  • Multi-channel JESD204B compliant clock solution
  • Low phase noise clocking for RF sampling ADC/DAC
  • Configurable phase synchronization to achieve low skew in multi-channel system
  • Supports TI’s high-speed converter and capture cards (ADC12DJ3200EVM, TSW14J56 / TSW14J57)

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDUD80A.PDF (2105 K)

Reference design overview and verified performance test data

TIDRR75A.PDF (1786 K)

Detailed schematic diagram for design layout and components

TIDRR76A.PDF (696 K)

Detailed schematic diagram for design layout and components

TIDRR77A.PDF (193 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRR78A.PDF (44 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRR79A.PDF (1084 K)

Detailed overview of design layout for component placement

TIDRR80A.PDF (644 K)

Detailed overview of design layout for component placement

TIDRR83A.ZIP (8944 K)

Files used for 3D models or 2D drawings of IC components

TIDRR84A.ZIP (7976 K)

Files used for 3D models or 2D drawings of IC components

TIDCDH9A.ZIP (6571 K)

Design file that contains information on physical board layer of design PCB

TIDCDI0A.ZIP (2080 K)

Design file that contains information on physical board layer of design PCB

TIDRR81A.PDF (7470 K)

PCB layer plot file used for generating PCB design layout

TIDRR82A.PDF (4389 K)

PCB layer plot file used for generating PCB design layout

Products

Includes TI products in the design and potential alternatives.

AND gates

SN74LVC1G08Single 2-input, 1.65-V to 5.5-V AND gate

Data sheet document-pdfAcrobat PDF
Analog switches & muxes

SN74CBTLV32573.3-V, 2:1 (SPDT), 4-channel analog switch with partial-power-down mode

Data sheet document-pdfAcrobat PDF open-in-new HTML
Analog switches & muxes

TMUX15745-V, 2:1 (SPDT), 4-channel analog switch with powered-off protection & 1.8-V input logic

Data sheet document-pdfAcrobat PDF open-in-new HTML
Buck converters (integrated switch)

TPS543182.95V to 6V Input, 3A Synchronous Step-Down SWIFT™ Converter

Data sheet document-pdfAcrobat PDF open-in-new HTML
Clock buffers

LMK003043.1-GHz differential clock buffer/level translator with 4 configurable outputs

Data sheet document-pdfAcrobat PDF open-in-new HTML
Clock jitter cleaners & synchronizers

LMK04828Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Data sheet document-pdfAcrobat PDF open-in-new HTML
High-speed ADCs (>10MSPS)

ADC08DJ32008-Bit, Dual 3.2-GSPS or Single 6.4-GSPS, RF-Sampling Analog-to-Digital Converter (ADC)

Data sheet document-pdfAcrobat PDF open-in-new HTML
High-speed ADCs (>10MSPS)

ADC12DJ270012-bit, dual 2.7-GSPS or single 5.4-GSPS, RF-sampling analog-to-digital converter (ADC)

Data sheet document-pdfAcrobat PDF open-in-new HTML
High-speed ADCs (>10MSPS)

ADC12DJ320012-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC)

Data sheet document-pdfAcrobat PDF open-in-new HTML
LVDS, M-LVDS & PECL ICs

DS90LV028AQ-Q1Automotive LVDS dual differential line receiver

Data sheet document-pdfAcrobat PDF open-in-new HTML
Linear & low-dropout (LDO) regulators

TLV702300-mA, high-PSRR, low-IQ, low-dropout voltage regulator with enable

Data sheet document-pdfAcrobat PDF open-in-new HTML
Linear & low-dropout (LDO) regulators

TPS7A471-A, 36-V, low-noise, high-PSRR, low-dropout voltage regulator with enable

Data sheet document-pdfAcrobat PDF open-in-new HTML
Linear & low-dropout (LDO) regulators

TPS7A83002-A, low-VIN, low-2-A, low-VIN, low-noise, ultra-low-dropout voltage regulator with power good wi

Data sheet document-pdfAcrobat PDF open-in-new HTML
N-channel MOSFETs

CSD15571Q220-V, N channel NexFET™ power MOSFET, single SON 2 mm x 2 mm, 19.2 mOhm

Data sheet document-pdfAcrobat PDF
Noninverting buffers & drivers

SN74LVC1G125Single 1.65-V to 5.5-V buffer with 3-state outputs

Data sheet document-pdfAcrobat PDF open-in-new HTML
Oscillators

LMK61E2156.250-MHz, ±50 ppm, ultra-low jitter, integrated EEPROM, fully programmable oscillator

Data sheet document-pdfAcrobat PDF open-in-new HTML
RF PLLs & synthesizers

LMX259415-GHz wideband PLLatinum™ RF synthesizer with phase synchronization and JESD204B support

Data sheet document-pdfAcrobat PDF open-in-new HTML
eFuses & hot swap controllers

TPS259254.5-V to 5.5-V, 30mΩ, 2-5A eFuse

Data sheet document-pdfAcrobat PDF open-in-new HTML

Start development

Software

GUI for evaluation module (EVM)

HSDC TID GUI (Rev. B) – TIDCDR5B.ZIP (15774 K)

Technical documentation

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Type Title Date
* Design guide Multichannel JESD204B 15-GHz Clocking Reference Design (Rev. A) Jun. 14, 2017
Technical article Step-by-step considerations for designing wide-bandwidth multichannel systems Jun. 04, 2019
Technical article Preparing for 5G applications: sync your multichannel JESD204B data acquisition systems up to 15 GHz Aug. 28, 2017

Related design resources

Hardware development

EVALUATION BOARD
ADC12DJ3200EVM ADC12DJ3200 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling ADC evaluation module TSW14J56EVM Data capture/pattern generator: data converter EVM with 8 JESD204B lanes from 0.6-12.5Gbps

Reference designs

REFERENCE DESIGN
TIDA-01022 Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems TIDA-01023 High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers TIDA-01024 High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers

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