TIDA-01024

High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers

TIDA-01024

Design files

Overview

High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports scaling up JESD204B synchronized clocks in daisy chain configuration. This design provides multichannel JESD204B clocks using TI’s LMK04828 clock jitter cleaner and LMX2594 wideband PLL with integrated VCOs to achieve clock-to-clock skew of <10 ps. This design is tested with TI’s ADC12DJ3200 EVMs at 3 GSPS, and a channel-to-channel skew of < 50 ps is achieved with improved SNR performance. All key design theories are described to guide users through the part selection process and design optimization. Finally, schematics, board layouts, hardware testing, and test results are included.

Features
  • High frequency (GSPS) sample clock generation
  • High channel count and scalable JESD204B compliant clock solution
  • Low phase noise clocking for RF sampling ADC/DAC
  • Configurable phase synchronization to achieve low skew in multi-channel system
  • Supports TI’s high-speed converter and capture cards (ADC12DJ3200EVM, TSW14J56 / TSW14J57)

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDUDS1.PDF (968 K)

Reference design overview and verified performance test data

TIDRV60.PDF (1785 K)

Detailed schematic diagram for design layout and components

TIDRV61.PDF (1228 K)

Detailed schematic diagram for design layout and components

TIDRV62.PDF (193 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRV63.PDF (94 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRV64.PDF (1082 K)

Detailed overview of design layout for component placement

TIDRV65.PDF (644 K)

Detailed overview of design layout for component placement

TIDRV68.ZIP (16987 K)

Files used for 3D models or 2D drawings of IC components

TIDRV69.ZIP (7976 K)

Files used for 3D models or 2D drawings of IC components

TIDCED9.ZIP (6569 K)

Design file that contains information on physical board layer of design PCB

TIDCEE0.ZIP (2080 K)

Design file that contains information on physical board layer of design PCB

TIDRV66.PDF (7468 K)

PCB layer plot file used for generating PCB design layout

TIDRV67.PDF (4389 K)

PCB layer plot file used for generating PCB design layout

Products

Includes TI products in the design and potential alternatives.

AND gates

SN74LVC1G08Single 2-input, 1.65-V to 5.5-V AND gate

Data sheet document-pdfAcrobat PDF
Analog switches & muxes

SN74CBTLV32573.3-V, 2:1 (SPDT), 4-channel analog switch with partial-power-down mode

Data sheet document-pdfAcrobat PDF open-in-new HTML
Analog switches & muxes

SN74LVC2G535-V, 2:1 (SPDT), 1-channel general-purpose analog switch (available in the NanoFree™ package)

Data sheet document-pdfAcrobat PDF open-in-new HTML
Analog switches & muxes

TMUX15745-V, 2:1 (SPDT), 4-channel analog switch with powered-off protection & 1.8-V input logic

Data sheet document-pdfAcrobat PDF open-in-new HTML
Buck converters (integrated switch)

TPS543182.95V to 6V Input, 3A Synchronous Step-Down SWIFT™ Converter

Data sheet document-pdfAcrobat PDF open-in-new HTML
Clock buffers

LMK003043.1-GHz differential clock buffer/level translator with 4 configurable outputs

Data sheet document-pdfAcrobat PDF open-in-new HTML
Clock jitter cleaners & synchronizers

LMK04828Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Data sheet document-pdfAcrobat PDF open-in-new HTML
Digital temperature sensors

LM95233±2°C Dual Remote and Local Temperature Sensor with TruTherm Technology and SMBus Interface

Data sheet document-pdfAcrobat PDF
High-speed ADCs (>10MSPS)

ADC12DJ320012-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC)

Data sheet document-pdfAcrobat PDF open-in-new HTML
LVDS, M-LVDS & PECL ICs

DS90LV028AQ-Q1Automotive LVDS dual differential line receiver

Data sheet document-pdfAcrobat PDF open-in-new HTML
Linear & low-dropout (LDO) regulators

TLV702300-mA, high-PSRR, low-IQ, low-dropout voltage regulator with enable

Data sheet document-pdfAcrobat PDF open-in-new HTML
Linear & low-dropout (LDO) regulators

TPS7A471-A, 36-V, low-noise, high-PSRR, low-dropout voltage regulator with enable

Data sheet document-pdfAcrobat PDF open-in-new HTML
Linear & low-dropout (LDO) regulators

TPS7A83002-A, low-VIN, low-noise, ultra-low-dropout voltage regulator with power good with high-accuracy

Data sheet document-pdfAcrobat PDF open-in-new HTML
Linear & low-dropout (LDO) regulators

TPS7A90500-mA, low-noise, high-PSRR, adjustable ultra-low-dropout voltage regulator with high-accuracy

Data sheet document-pdfAcrobat PDF open-in-new HTML
N-channel MOSFETs

CSD15571Q220-V, N channel NexFET™ power MOSFET, single SON 2 mm x 2 mm, 19.2 mOhm

Data sheet document-pdfAcrobat PDF
Oscillators

LMK61E2156.250-MHz, ±50 ppm, ultra-low jitter, integrated EEPROM, fully programmable oscillator

Data sheet document-pdfAcrobat PDF open-in-new HTML
RF PLLs & synthesizers

LMX259415-GHz wideband PLLatinum™ RF synthesizer with phase synchronization and JESD204B support

Data sheet document-pdfAcrobat PDF open-in-new HTML
eFuses & hot swap controllers

TPS259254.5-V to 5.5-V, 30mΩ, 2-5A eFuse

Data sheet document-pdfAcrobat PDF open-in-new HTML

Start development

Software

GUI for evaluation module (EVM)

TIDA-01024 HSDC TID GUI – TIDCEE1.ZIP (15772 K)

Technical documentation

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Type Title Date
* Design guide High-Channel-Count JESD204B Daisy-Chain Clock Reference Design for RADAR and 5G Nov. 28, 2017
Technical article Step-by-step considerations for designing wide-bandwidth multichannel systems Jun. 04, 2019

Related design resources

Hardware development

EVALUATION BOARD
ADC12DJ3200EVM ADC12DJ3200 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling ADC evaluation module TSW14J56EVM Data capture/pattern generator: data converter EVM with 8 JESD204B lanes from 0.6-12.5Gbps

Reference designs

REFERENCE DESIGN
TIDA-01021 Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers TIDA-01022 Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems TIDA-01023 High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers

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