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LMK04832-SP

ACTIVE

Radiation-hardened-assured (RHA), ultra-low-noise, 3.2-GHz, 15-output clock jitter cleaner

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Data sheet

LMK04832-SP

ACTIVE
Data sheet Order now

Product details

Number of input channels 3 Number of outputs 15 RMS jitter (fs) 54 Features +/-25ppm, 0 Delay, Integrated VCO, JESD204B, Loss of signal detection, Manual/auto switch, Programmable Delay, SPI Output frequency (max) (MHz) 3255 Output type CML, HSDS, LVCMOS, LVDS, LVPECL Input type HCSL, LVCMOS, LVCMOS (REF_CLK), LVDS, LVPECL, LVPECL (VCXO_CLK) Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Operating temperature range (°C) -55 to 125
Number of input channels 3 Number of outputs 15 RMS jitter (fs) 54 Features +/-25ppm, 0 Delay, Integrated VCO, JESD204B, Loss of signal detection, Manual/auto switch, Programmable Delay, SPI Output frequency (max) (MHz) 3255 Output type CML, HSDS, LVCMOS, LVDS, LVPECL Input type HCSL, LVCMOS, LVCMOS (REF_CLK), LVDS, LVPECL, LVPECL (VCXO_CLK) Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Operating temperature range (°C) -55 to 125
CFP (HBE) 64 118.81 mm² 10.9 x 10.9
  • SMD #5962R1723701VXC
    • Total ionizing dose 100 krad (ELDRS-free)
    • SEL immune >120 MeV × cm2/mg
    • SEFI immune >120 MeV × cm2/mg
  • Maximum clock output frequency: 3255 MHz
  • Multi-mode: dual PLL, single PLL, and clock distribution
  • 6-GHz external VCO or distribution input
  • Ultra-low noise, at 2500 MHz:
    • 54-fs RMS jitter (12 kHz to 20 MHz)
    • 64-fs RMS jitter (100 Hz to 20 MHz)
    • –157.6-dBc/Hz noise floor
  • Ultra-low noise, at 3200 MHz:
    • 61-fs RMS jitter (12 kHz to 20 MHz)
    • 67-fs RMS jitter (100 Hz to 100 MHz)
    • –156.5-dBc/Hz noise floor
  • PLL2
    • PLL FOM of –230 dBc/Hz
    • PLL 1/f of –128 dBc/Hz
    • Phase detector rate up to 320 MHz
    • Two integrated VCOs: 2440 to 2600 MHz and 2945 to 3255 MHz
  • Up to 14 differential device clocks
    • CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS programmable outputs
  • Up to 1 buffered VCXO/XO output
    • LVPECL, LVDS, 2xLVCMOS programmable
  • 1-1023 CLKout divider
  • 1-8191 SYSREF divider
  • 25-ps step analog delay for SYSREF clocks
  • Digital delay and dynamic digital delay for device clock and SYSREF
  • Holdover mode with PLL1
  • 0-delay with PLL1 or PLL2
  • Ambient temperature range: –55 °C to 125 °C
  • SMD #5962R1723701VXC
    • Total ionizing dose 100 krad (ELDRS-free)
    • SEL immune >120 MeV × cm2/mg
    • SEFI immune >120 MeV × cm2/mg
  • Maximum clock output frequency: 3255 MHz
  • Multi-mode: dual PLL, single PLL, and clock distribution
  • 6-GHz external VCO or distribution input
  • Ultra-low noise, at 2500 MHz:
    • 54-fs RMS jitter (12 kHz to 20 MHz)
    • 64-fs RMS jitter (100 Hz to 20 MHz)
    • –157.6-dBc/Hz noise floor
  • Ultra-low noise, at 3200 MHz:
    • 61-fs RMS jitter (12 kHz to 20 MHz)
    • 67-fs RMS jitter (100 Hz to 100 MHz)
    • –156.5-dBc/Hz noise floor
  • PLL2
    • PLL FOM of –230 dBc/Hz
    • PLL 1/f of –128 dBc/Hz
    • Phase detector rate up to 320 MHz
    • Two integrated VCOs: 2440 to 2600 MHz and 2945 to 3255 MHz
  • Up to 14 differential device clocks
    • CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS programmable outputs
  • Up to 1 buffered VCXO/XO output
    • LVPECL, LVDS, 2xLVCMOS programmable
  • 1-1023 CLKout divider
  • 1-8191 SYSREF divider
  • 25-ps step analog delay for SYSREF clocks
  • Digital delay and dynamic digital delay for device clock and SYSREF
  • Holdover mode with PLL1
  • 0-delay with PLL1 or PLL2
  • Ambient temperature range: –55 °C to 125 °C

The LMK04832-SP is a high performance clock conditioner with JEDEC JESD204B support for space applications.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

The LMK04832-SP can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.

The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover allows the LMK04832-SP to provide flexible high performance clocking trees.

The LMK04832-SP comes in a 10.9-mm × 10.9-mm, 64-pin CFP package.

The LMK04832-SP is a high performance clock conditioner with JEDEC JESD204B support for space applications.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

The LMK04832-SP can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.

The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover allows the LMK04832-SP to provide flexible high performance clocking trees.

The LMK04832-SP comes in a 10.9-mm × 10.9-mm, 64-pin CFP package.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet LMK04832-SP Space Grade Ultra-Low-Noise JESD204B Dual-Loop Clock Jitter Cleaner datasheet (Rev. C) PDF | HTML 10 Nov 2022
* Radiation & reliability report LMK04832-SP Single-Event Effects Report 13 May 2021
* Radiation & reliability report LMK04832-SP ELDRS Characterization Report 19 Nov 2020
* Radiation & reliability report LMK04832-SP TID RLAT Report V009FOGX Wafer 21 PDF | HTML 19 Nov 2020
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML 17 Jun 2025
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. B) PDF | HTML 10 Jun 2025
Application note Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A) PDF | HTML 11 Apr 2025
Selection guide TI Space Products (Rev. K) 04 Apr 2025
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) 20 Feb 2025
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 19 Oct 2022
More literature Total Ionizing Dose and Single Event Effects Test Results of LMK04832-SP 18 Jul 2021
E-book Radiation Handbook for Electronics (Rev. A) 21 May 2019

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK04832EVM-CVAL — LMK04832-SP evaluation module for ultra-low-noise, dual-loop, JESD204B clock jitter cleaner

The LMK04832EVM-CVAL evaluation module (EVM) provides a platform to evaluate the performance and
features of the LMK04832-SP space grade ultra-low-noise JESD204B dual-loop clock jitter cleaner
from Texas Instruments.
User guide: PDF | HTML
Not available on TI.com
Support software

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

Supported products & hardware

Supported products & hardware
Download options
Simulation model

LMK04832-SP IBIS model (Rev. A)

SNAM242A.ZIP (168 KB) - IBIS Model
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Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Design now
Design tool

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware

Supported products & hardware
Download options
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Reference designs

TIDA-010191 — Space-grade multichannel JESD204B 15-GHz clocking reference design

Phased-array antennas and digital beamforming are key technologies that will boost the performance of future spaceborne radar imaging and broadband satellite communication systems. Digital beamforming, unlike analog beamforming, typically requires a set of data converters per antenna element. (...)
Design guide: PDF
Package Pins CAD symbols, footprints & 3D models
CFP (HBE) 64 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
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  • Lead finish/Ball material
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  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

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