TIDA-01023
High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers
TIDA-01023
Overview
High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports high channel count JESD204B synchronized clocks using one master and multiple slave clocking devices. This design provides multichannel JESD204B clocks using TI’s LMK04828 clock jitter cleaner and LMX2594 wideband PLL with integrated VCOs to achieve clock-to-clock skew of <10 ps. This design is tested with TI’s ADC12DJ3200 EVMs at 3 GSPS, and a channel-to-channel skew of < 50 ps is achieved with improved SNR performance. All key design theories are described to guide users through the part selection process and design optimization. Finally, schematics, board layouts, hardware testing, and test results are included.
Features
- High frequency (GSPS) sample clock generation
- High channel count and scalable JESD204B compliant clock solution
- Low phase noise clocking for RF sampling ADC/DAC
- Configurable phase synchronization to achieve low skew in multi-channel system
- Supports TI’s high-speed converter and capture cards (ADC12DJ3200EVM, TSW14J56 / TSW14J57)
Communications equipment
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
Design files & products
Design files
Download ready-to-use system files to speed your design process.
TIDUDS0.PDF (1307 K)
Reference design overview and verified performance test data
TIDRV50.PDF (1785 K)
Detailed schematic diagram for design layout and components
TIDRV51.PDF (1228 K)
Detailed schematic diagram for design layout and components
TIDRV52.PDF (193 K)
Complete listing of design components, reference designators, and manufacturers/part numbers
TIDRV53.PDF (94 K)
Complete listing of design components, reference designators, and manufacturers/part numbers
TIDRV54.PDF (1082 K)
Detailed overview of design layout for component placement
TIDRV55.PDF (644 K)
Detailed overview of design layout for component placement
TIDRV58.ZIP (17783 K)
Files used for 3D models or 2D drawings of IC components
TIDRV59.ZIP (7976 K)
Files used for 3D models or 2D drawings of IC components
TIDCED6.ZIP (6569 K)
Design file that contains information on physical board layer of design PCB
TIDCED7.ZIP (2080 K)
Design file that contains information on physical board layer of design PCB
TIDRV56.PDF (7468 K)
PCB layer plot file used for generating PCB design layout
TIDRV57.PDF (4389 K)
PCB layer plot file used for generating PCB design layout
Products
Includes TI products in the design and potential alternatives.
Analog switches & muxes
SN74CBTLV3257 — 3.3-V, 2:1 (SPDT), 4-channel analog switch with partial-power-down mode
Data sheet: PDF | HTMLAnalog switches & muxes
SN74LVC2G53 — 5-V, 2:1 (SPDT), 1-channel general-purpose analog switch (available in the NanoFree™ package)
Data sheet: PDF | HTMLHigh-speed ADCs (≥10 MSPS)
ADC12DJ3200 — 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC)
Data sheet: PDF | HTMLLVDS, M-LVDS & PECL ICs
DS90LV028AQ-Q1 — Automotive LVDS dual differential line receiver
Data sheet: PDF | HTMLN-channel MOSFETs
CSD15571Q2 — 20-V, N channel NexFET™ power MOSFET, single SON 2 mm x 2 mm, 19.2 mOhm
Data sheet: PDFStart development
Technical documentation
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| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | High-Channel-Count JESD204B Clock Generation Ref Design for RADAR and 5G Testers | Oct. 26, 2017 | |
| Technical article | Step-by-step considerations for designing wide-bandwidth multichannel systems | Jun. 04, 2019 |
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