Clock Jitter Cleaners - improve overall system performance
Industry’s lowest power/jitter JESD204B compliant jitter cleaners
Features include: Ultra low jitter - 65fs typ 12k-20M @ 122.88 MHz and 50fs typ 12k-20M @ 1966.08 MHz, ultra low inband phase noise through leading BiCMOS technology
Industry’s first and most popular JESD204B jitter cleaner family, LMK0482x, that supports JESD204B and non-JESD204B applications with a single device. Full SYSREF support reduces SoC complexity and cost. Multiple SYSREF frequencies from one device.
PLLATINUM dual phase locked loop (PLL) concept reduces cost and improves performance. The innovative semi-digital PLL technique offers best performance, while integrating PLL loop filter components and supporting <5 Hz loop bandwidth.
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|Device||Description||# of Outputs||Output Frequency (Max) (MHz)||# of Inputs||RMS Jitter (fs)*||Applications||Special Features|
|LMK04610||High performance dual loop jitter cleaner||10 to 16||2000||2 to 4||65||Wireless, Industrial||Cascaded PLL, SPI, Holdover mode, 105C PCB temp support, JESD204B SYSREF support - Multiple SYSREF frequencies from one device, Fully integrated loop filter - <5Hz loop bandwidth, Integrated LDOs for 70dBc PSRR, Low power with 0.88W @ 10 outputs running|
|LMK04832||Ultra Low Noise 3.2GHz Jitter Cleaner, Clock Generator and Distributor||14||3202||3||88||Wireless, Industrial||3.3V Vcc/Vdd, JESD204B SYSREF Generation, Holdover mode, Jitter Cleaner, Manual and auto switching between inputs, SPI, uWire|
|LMK04808||High performance dual loop jitter cleaner||14||3072||2||111||Wireless, Industrial||Cascaded PLL, SPI/uWire, Holdover mode, Int. XTAL oscillator on PLL1|
|LMK04906||High performance dual loop jitter cleaner||6||2600||3||100||Wireless, Industrial||Cascaded PLL, SPI/uWire, Holdover mode, Int. XTAL oscillator on PLL1|
|CDCM7005-SP||Space grade single loop jitter cleaner||5||1500||2||NA - single loop||Space||Single PLL, SPI, Rad-Tolerant Class V|
*12kHz to 20MHz
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WEBENCH® Clock Architect
TI's WEBENCH Clock Architect online design tool makes the designer’s life easier by generating complete clock-tree solutions. Multiple solutions are generated, each optimized for performance, cost or board space.