SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Please refer to the AM62Ax DDR Board Design and Layout Guidelines application note for detailed information on DDR interface connections to LPDDR4 and DDR4 memory devices
Table 9-1 describes the DDRSS0 I/O signals used for connection to SDRAM devices.
Module Pin | Device Level Signal | I/O(1) | Description |
---|---|---|---|
RESETN | DDR0_RESET0_n | O | SDRAM reset |
CK | DDR0_CK0 | O | SDRAM differential clock pair |
CKN | DDR0_CK0_n | O | |
ALERTN | DDR0_ALERT_n | IO | SDRAM parity error output |
A[13-0] | DDR0_A[13-0] | O | SDRAM address and command bus |
WEN | DDR0_WE_n | O | SDRAM write enable |
CASN/CSN[3] | DDR0_CAS_n/DDR0_CS3_n | O | SDRAM column address strobe (DDR4). SDRAM chip select (LPDDR4) |
RASN/CSN[2] | DDR0_RAS_n/DDR0_CS2_n | O | SDRAM row address strobe(DDR4). SDRAM chip select(LPDDR4) |
ACTN | DDR0_ACT_n | O | SDRAM activate |
BA[1-0] | DDR0_BA[1-0] | O | SDRAM bank address |
BG[1-0] | DDR0_BG[1-0] | O | SDRAM bank group |
PAR | DDR0_PAR | O | SDRAM command parity |
CSN[1-0] | DDR0_CS[1-0]_n | O | SDRAM chip select |
ODT[1-0] | DDR0_ODT[1-0] | O | SDRAM on-die termination |
CKE[1-0] | DDR0_CKE[1-0] | O | SDRAM CKE |
DQ[31-0] | DDR0_DQ[31-0] | IO | SDRAM data bus |
DM[3-0] | DDR0_DM[3-0] | IO | SDRAM data and mask/DBI |
DQS[3-0] | DDR0_DQS[3-0] | IO | SDRAM data strobe |
DQSN[3-0] | DDR0_DQS[3-0]_n | IO | SDRAM data strobe invert |
For more information about device level signals (pull-up/down resistors, buffer type, multiplexing and others), see tables Pin Attributes and Pin Multiplexing in the device-specific Datasheet.