SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Table 5-25 shows configuration pins assignment to functions when boot mode is the Ethernet RGMII mode.
BOOTMODE Pins | Field | Value | Description |
---|---|---|---|
9 | Clkout | 0 | Must be set to 0 to choose external clock |
1 | Reserved | ||
8 | Delay | 0 | Must be set to 0 for RGMII with internal Tx delay |
1 | Reserved | ||
7 | Link info | 0 | MDIO PHY scan used for link parameters. |
1 | Link parameters programmed by the ROM |
Table 5-26 shows configuration pins assignment to functions when boot mode is the Ethernet RMII mode.
BOOTMODE Pins | Field | Value | Description |
---|---|---|---|
9 | Clkout | 0 | 50 MHz clock not generated on CLKOUT0 |
1 | 50 MHz clock generated on CLKOUT0 | ||
8 | Clk src | 0 | External clock source for RMII1_REF_CLK |
1 | Internal clock source for RMII1_REF_CLK | ||
7 | RMII | 0 | This bit must be set to 0 |
1 | Reserved |
BOOTMODE Pin 9 (Clk out) | BOOTMODE Pin 8 (Clk src) | Description |
---|---|---|
0 | 0 | 50MHz external source to RMII_REF_CLK and to external Ethernet PHY input clock (CLKOUT0 is unused) These are the recommended settings |
0 | 1 | Not a valid configuration |
1 | 0 | CLKOUT0 is configured to 50MHz and connect to both RMII1_REF_CLK and to external Ethernet PHY input clock |
1 | 1 | Not a valid configuration |
Table 5-28 shows configuration pins assignment to functions when the backup boot mode Ethernet. The Interface configuration field chooses which interface will be used (RGMII or RMII)
BOOTMODE Pins | Field | Value | Description |
---|---|---|---|
13 | Interface | 0 | RGMII with internal TX delay |
1 | RMII with external clock source |
Table 5-29 summarizes the RGMII pin configuration done by ROM code for Ethernet boot device on RGMII port.
Device Pin | Module Signal | Pull Enable | Pull Direction | Driver Index | Rx En/Dis | Pinmux Sel | Pad Configuration Register |
---|---|---|---|---|---|---|---|
RGMII1_TX_CTL | RGMII1_TX_CTL | Disable | NA | 0 | Disable | 0 | PADCONFIG75 |
RGMII1_TXC | RGMII1_TXC | Disable | NA | 0 | Disable | 0 | PADCONFIG76 |
RGMII1_TD0 | RGMII1_TD0 | Disable | NA | 0 | Disable | 0 | PADCONFIG77 |
RGMII1_TD1 | RGMII1_TD1 | Disable | NA | 0 | Disable | 0 | PADCONFIG78 |
RGMII1_TD2 | RGMII1_TD2 | Disable | NA | 0 | Disable | 0 | PADCONFIG79 |
RGMII1_TD3 | RGMII1_TD3 | Disable | NA | 0 | Disable | 0 | PADCONFIG80 |
RGMII1_RX_CTL | RGMII1_RX_CTL | Disable | NA | 0 | Enable | 0 | PADCONFIG81 |
RGMII1_RXC | RGMII1_RXC | Disable | NA | 0 | Enable | 0 | PADCONFIG82 |
RGMII1_RD0 | RGMII1_RD0 | Disable | NA | 0 | Enable | 0 | PADCONFIG83 |
RGMII1_RD1 | RGMII1_RD1 | Disable | NA | 0 | Enable | 0 | PADCONFIG84 |
RGMII1_RD2 | RGMII1_RD2 | Disable | NA | 0 | Enable | 0 | PADCONFIG85 |
RGMII1_RD3 | RGMII1_RD3 | Disable | NA | 0 | Enable | 0 | PADCONFIG86 |
MDIO0_MDIO | MDIO0_MDIO | Disable | NA | 0 | Enable | 0 | PADCONFIG87 |
MDIO0_MDC | MDIO0_MDC | Disable | NA | 0 | Disable | 0 | PADCONFIG88 |
Table 5-30 summarizes the RMII pin configuration done by ROM code for Ethernet boot device on RMII port.
Device Pin | Module Signal | Pull Enable | Pull Direction | Driver Index | Rx En/Dis | Pinmux Sel | Pad Configuration Register |
---|---|---|---|---|---|---|---|
RGMII1_RX_CTL | RMII1_RX_ER | Disable | NA | 0 | Enable | 1 | PADCONFIG81 |
RGMII1_RXC | RMII1_REF_CLK | Disable | NA | 0 | Enable | 1 | PADCONFIG82 |
RGMII1_RD0 | RMII1_RXD0 | Disable | NA | 0 | Enable | 1 | PADCONFIG83 |
RGMII1_RD1 | RMII1_RXD1 | Disable | NA | 0 | Enable | 1 | PADCONFIG84 |
RGMII1_TD0 | RMII1_TXD0 | Disable | NA | 0 | Disable | 1 | PADCONFIG77 |
RGMII1_TD1 | RMII1_TXD1 | Disable | NA | 0 | Disable | 1 | PADCONFIG78 |
RGMII1_TX_CTL | RMII1_TX_EN | Disable | NA | 0 | Disable | 1 | PADCONFIG75 |
RGMII1_TXC | RMII1_CRS_DV | Disable | NA | 0 | Enable | 1 | PADCONFIG76 |
RGMII1_TD3 | CLKOUT0 | Disable | NA | 0 | Disable | 1 | PADCONFIG_80 |
MDIO0_MDIO | MDIO0_MDIO | Disable | NA | 0 | Enable | 0 | PADCONFIG87 |
MDIO0_MDC | MDIO0_MDC | Disable | NA | 0 | Disable | 0 | PADCONFIG88 |