SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Bits | Field | Type | Reset | Description |
---|---|---|---|---|
31:0 | sts | r/w1ts | 0x0 |
This is the raw status of the events in Group M. Each bit corresponds to event Q where Q = M*32+Bit (Example: bit 0 is event M*32+0, bit 1 is M*32 + 1 etc…) Read: 0 – Inactive 1 – Active/Pending Write: 0 – No effect 1 – Set to Interrupt Raw Status |