SPRUJB3 March   2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1

1.   1
2.   Read This First
   1.     About This Manual
   2.     Related Documentation From Texas Instruments
   3.     Glossary
   4.     Support Resources
   5.     Export Control Notice
   6.     Release History
   7.     Trademarks
3. 1 Introduction
   1. 1.1 Overview
   2. 1.2 Module Allocation and Instances within Device Domains
   3. 1.3 Functional Block Diagram
   4. 1.4 Device MAIN Domain
      1. 1.4.1  Arm Cortex-A53 Subsystem (A53SS)
      2. 1.4.2  Arm Cortex-R5F Processor (R5FSS)
      3. 1.4.3  Deep Learning Accelerator (C7x256v)
      4. 1.4.4  Vision Pre-processing Accelerator
      5. 1.4.5  Depth and Motion Perception Accelerator
      6. 1.4.6  Mailbox (MAILBOX)
      7. 1.4.7  Spinlock (SPINLOCK)
      8. 1.4.8  DDR 32-bit Subsystem (DDR32)
      9. 1.4.9  Data Movement Subsystem (DMSS)
      10. 1.4.10 General Purpose Input/Output Interface (GPIO)
      11. 1.4.11 Inter-Integrated Circuit Interface (I2C)
      12. 1.4.12 Serial Peripheral Interface (SPI)
      13. 1.4.13 Universal Asynchronous Receiver/Transmitter (UART)
      14. 1.4.14 3-port Gigabit Ethernet Switch (CPSW3G)
      15. 1.4.15 Universal Serial Bus (USB) Subsystem 2.0
      16. 1.4.16 Universal Serial Bus 3.1 Subsystem (USBSS)
      17. 1.4.17 Serializer/Deserializer (SERDES)
      18. 1.4.18 Peripheral Component Interconnect Express Subsystem (PCIE)
      19. 1.4.19 Enhanced Pulse-Width Modulation Module (EPWM)
      20. 1.4.20 Enhanced Quadrature Encoder Pulse Module (EQEP)
      21. 1.4.21 Enhanced Capture Module (ECAP)
      22. 1.4.22 Controller Area Network (MCAN)
      23. 1.4.23 Flash Subsystem (FSS) with Octal Serial Peripheral Interface (OSPI)
      24. 1.4.24 General Purpose Memory Controller (GPMC)
      25. 1.4.25 Error Location Module (ELM)
      26. 1.4.26 Multi-Media Card/Secure Digital Interface (MMCSD)
      27. 1.4.27 Memory Cyclic Redundancy Check
      28. 1.4.28 Windowed Watchdog Timer/Real Time Interrupt
      29. 1.4.29 TIMER
      30. 1.4.30 Audio Tracking Logic
      31. 1.4.31 Camera Subsystem
      32. 1.4.32 Dual Clock Comparator
      33. 1.4.33 Error Signaling Module (ESM)
      34. 1.4.34 Multi-Channel Audio Serial Port (McASP)
      35. 1.4.35 Camera Streaming Interface Receiver (CSI-RX)
      36. 1.4.36 Display Subsystem (DSS)
      37. 1.4.37 Open LVDS Display Interface transmitter (OLDI-TX)
      38. 1.4.38 MIPI DPHY Receiver
      39. 1.4.39 MIPI DPHY Transmitter
      40. 1.4.40 Graphics Processing Unit
      41. 1.4.41 Video Accelerator (CODEC)
   5. 1.5 Device MCU Domain
      1. 1.5.1  Arm Cortex-R5F Processor (R5FSS)
      2. 1.5.2  MCU General Purpose Input/Output Interface (MCU_GPIO)
      3. 1.5.3  MCU Inter-Integrated Circuit Interface (MCU_I2C)
      4. 1.5.4  MCU Multi-channel Serial Peripheral Interface (MCU_SPI)
      5. 1.5.5  MCU Universal Asynchronous Receiver/Transmitter (MCU_UART)
      6. 1.5.6  MCU Windowed Watchdog Timer/Real Time Interrupt
      7. 1.5.7  WKUP TIMER
      8. 1.5.8  MCU Dual Clock Comparator
      9. 1.5.9  Memory Cyclic Redundancy Check
      10. 1.5.10 Controller Area Network (MCAN)
   6. 1.6 Device WKUP Domain
      1. 1.6.1 Arm Cortex-R5F Processor (R5FSS)
      2. 1.6.2 Inter-Integrated Circuit Interface (I2C)
      3. 1.6.3 Universal Asynchronous Receiver/Transmitter (UART)
      4. 1.6.4 MCU Error Signaling Module
      5. 1.6.5 Global Time Counter
      6. 1.6.6 Windowed Watchdog Timer/Real Time Interrupt
      7. 1.6.7 WKUP_TIMER
   7. 1.7 Device Identification
4. 2 Memory Map
   1. 2.1 MAIN Memory Map
   2. 2.2 MCU Memory Map
   3. 2.3 WKUP Memory Map
   4. 2.4 R5FSS0 Memory Map
   5. 2.5 MCU_R5FSS0 Memory Map
   6. 2.6 WKUP_R5FSS0 Memory Map
   7. 2.7 DMASS0 Memory Map
   8. 2.8 SMS0 Memory Map
   9. 2.9 SA3_SS0 Memory Map
5. 3 System Interconnect
   1. 3.1 System Interconnect Overview
      1. 3.1.1 Terminology
   2. 3.2 Domain Partition
   3. 3.3 Initiator/Target Connectivity
   4. 3.4 Coherency Features
      1. 3.4.1 IO Coherency Support
   5. 3.5 Performance Tuning
      1. 3.5.1 Latency Reduction
      2. 3.5.2 Using Quality of Service (QoS) MMR
         1. 3.5.2.1 QoS MMR Programming Guide
         2. 3.5.2.2 QoS Summary Tables
            1. 3.5.2.2.1  CODEC0_QoS_Map
            2. 3.5.2.2.2  DEBUGSS_WRAP0_QoS_Map
            3. 3.5.2.2.3  COMPUTE_CLUSTER0_QoS_Map
            4. 3.5.2.2.4  DSS0_QoS_Map
            5. 3.5.2.2.5  DSS1_QoS_Map
            6. 3.5.2.2.6  GICSS0_QoS_Map
            7. 3.5.2.2.7  GPU0_QoS_Map
            8. 3.5.2.2.8  MCU_R5FSS0_QoS_Map
            9. 3.5.2.2.9  MMCSD0_QoS_Map
            10. 3.5.2.2.10 WKUP_R5FSS0_QoS_Map
            11. 3.5.2.2.11 USB0_QoS_Map
            12. 3.5.2.2.12 USB1_QoS_Map
            13. 3.5.2.2.13 SA3_SS0_QoS_Map
            14. 3.5.2.2.14 MMCSD1_QoS_Map
            15. 3.5.2.2.15 MMCSD2_QoS_Map
   6. 3.6 Interconnect Debugging Feature
6. 4 Module Integration
   1. 4.1  Memory Controllers
      1. 4.1.1 DDR32 Subsystem (DDR32SS)
         1. 4.1.1.1 DDR32SS Not Supported Features
         2. 4.1.1.2 DDR32SS Module Allocations
         3. 4.1.1.3 Resets, Interrupts and Clocks
      2. 4.1.2 msram8kx256e
         1. 4.1.2.1 Module Allocations
         2. 4.1.2.2 Resets, Interrupts and Clocks
   2. 4.2  System Interconnect
      1. 4.2.1 CBASS
         1. 4.2.1.1 CBASS_AUDIO
            1. 4.2.1.1.1 Module Allocations
            2. 4.2.1.1.2 Resets, Interrupts, and Clocks
         2. 4.2.1.2 CBASS_RT_CFG
            1. 4.2.1.2.1 Module Allocations
            2. 4.2.1.2.2 Resets, Interrupts, and Clocks
         3. 4.2.1.3 CBASS_RT_DATA
            1. 4.2.1.3.1 Module Allocations
            2. 4.2.1.3.2 Resets, Interrupts, and Clocks
         4. 4.2.1.4 CBASS_RT_FW
            1. 4.2.1.4.1 Module Allocations
            2. 4.2.1.4.2 Resets, Interrupts, and Clocks
      2. 4.2.2 C7XV_RSWS_BS_LIMITER
         1. 4.2.2.1 Module Allocations
         2. 4.2.2.2 Resets, Interrupts, and Clocks
      3. 4.2.3 JPGENC_RS_BW_LIMITER
         1. 4.2.3.1 Module Allocations
         2. 4.2.3.2 Resets, Interrupts, and Clocks
      4. 4.2.4 JPGENC_WS_BW_LIMITER
         1. 4.2.4.1 Module Allocations
         2. 4.2.4.2 Resets, Interrupts, and Clocks
      5. 4.2.5 GPU_RS_BW_LIMITER
         1. 4.2.5.1 Module Allocations
         2. 4.2.5.2 Resets, Interrupts, and Clocks
      6. 4.2.6 GPU_WS_BW_LIMITER
         1. 4.2.6.1 Module Allocations
         2. 4.2.6.2 Resets, Interrupts, and Clocks
      7. 4.2.7 VPAC_RSWS_BW_LIMITER
         1. 4.2.7.1 Module Allocations
         2. 4.2.7.2 Resets, Interrupts, and Clocks
   3. 4.3  Processors and Accelerators
      1. 4.3.1 Arm Cortex A53 Subsystem (A53SS)
         1. 4.3.1.1 A53SS Unsupported Features
         2. 4.3.1.2 Module Allocations
         3. 4.3.1.3 Resets, Interrupts, and Clocks
      2. 4.3.2 WAVE 521CL - CODEC
         1. 4.3.2.1 WAVE521CL Unsupported Features
         2. 4.3.2.2 Module Allocations
         3. 4.3.2.3 Resets, Interrupts, and Clocks
      3. 4.3.3 Arm Cortex R5F Subsystem (R5FSS)
         1. 4.3.3.1 Module Allocations
         2. 4.3.3.2 Resets, Interrupts, and Clocks
         3. 4.3.3.3 Arm Cortex R5F Subsystem (MCU_R5FSS)
            1. 4.3.3.3.1 MCU_R5FSS Unsupported Features
            2. 4.3.3.3.2 Module Allocations
            3. 4.3.3.3.3 Resets, Interrupts, and Clocks
         4. 4.3.3.4 R5FSS_CORE0
            1. 4.3.3.4.1 Module Allocations
            2. 4.3.3.4.2 Resets, Interrupts, and Clocks
         5. 4.3.3.5 R5FSS_COMMON0
            1. 4.3.3.5.1 Module Allocations
            2. 4.3.3.5.2 Resets, Interrupts, and Clocks
      4. 4.3.4 Vision Pre-processing Accelerator (VPAC)
         1. 4.3.4.1 Module Allocations
         2. 4.3.4.2 Resets, Interrupts, and Clocks
      5. 4.3.5 Depth and Motion Perception Accelerator (DMPAC)
         1. 4.3.5.1 Module Allocations
         2. 4.3.5.2 Resets, Interrupts, and Clocks
      6. 4.3.6 JPGENC
         1. 4.3.6.1 Module Allocations
         2. 4.3.6.2 Resets, Interrupts, and Clocks
      7. 4.3.7 C7X256V
         1. 4.3.7.1 Module Allocations
         2. 4.3.7.2 Resets, Interrupts, and Clocks
         3. 4.3.7.3 C7X256V_C7XV_CORE_0
            1. 4.3.7.3.1 Module Allocations
            2. 4.3.7.3.2 Resets, Interrupts, and Clocks
         4. 4.3.7.4 C7X256V_CORE0
            1. 4.3.7.4.1 Module Allocations
            2. 4.3.7.4.2 Resets, Interrupts, and Clocks
         5. 4.3.7.5 C7X256V_CLEC
            1. 4.3.7.5.1 Module Allocations
            2. 4.3.7.5.2 Resets, Interrupts, and Clocks
         6. 4.3.7.6 C7X256V_PBIST
            1. 4.3.7.6.1 Module Allocations
            2. 4.3.7.6.2 Resets, Interrupts, and Clocks
      8. 4.3.8 Graphics Processing Unit (GPU)
         1. 4.3.8.1 GPU Unsupported Features
         2. 4.3.8.2 Module Allocations
         3. 4.3.8.3 Resets, Interrupts, and Clocks
   4. 4.4  Interprocessor Communication
      1. 4.4.1 Mailbox
         1. 4.4.1.1 Mailbox Unsupported Features
         2. 4.4.1.2 Module Allocations
         3. 4.4.1.3 Resets, Interrupts, and Clocks
      2. 4.4.2 Spinlock
         1. 4.4.2.1 SPINLOCK Unsupported Features
         2. 4.4.2.2 Module Allocations
         3. 4.4.2.3 Resets, Interrupts, and Clocks
   5. 4.5  Device Configuration
      1. 4.5.1 Control Module (CTRL_MMR)
         1. 4.5.1.1 Module Allocations
         2. 4.5.1.2 Resets, Interrupts, and Clocks
         3. 4.5.1.3 Module Allocations
         4. 4.5.1.4 Resets, Interrupts, and Clocks
      2. 4.5.2 Voltage and Thermal Manager (VTM)
         1. 4.5.2.1 Module Allocations
         2. 4.5.2.2 Resets, Interrupts, and Clocks
      3. 4.5.3 Power Sleep Controller (PSC)
         1. 4.5.3.1 Module Allocations
         2. 4.5.3.2 Resets, Interrupts, and Clocks
      4. 4.5.4 Clocking
         1. 4.5.4.1 pllfracf2_ssmod_16fft
            1. 4.5.4.1.1 Module Allocations
            2. 4.5.4.1.2 Resets, Interrupts, and Clocks
   6. 4.6  Interrupts
      1. 4.6.1 TIMESYNC_EVENT_INTROUTER
         1. 4.6.1.1 Module Allocations
         2. 4.6.1.2 Resets, Interrupts, and Clocks
      2. 4.6.2 Generic Interrupt Controller Subsystem (GICSS)
         1. 4.6.2.1 GICSS Unsupported Features
         2. 4.6.2.2 Module Allocation
         3. 4.6.2.3 Resets, Interrupts, and Clocks
   7. 4.7  Data Movement Architecture
      1. 4.7.1 Data Movement Subsystem (DMSS)
         1. 4.7.1.1 DMSS Unsupported Features
         2. 4.7.1.2 Module Allocations
         3. 4.7.1.3 Global Event Map
         4. 4.7.1.4 PSI-L System Thread Map
      2. 4.7.2 Block Copy DMA (BCDMA)
         1. 4.7.2.1 Block Copy DMA (BCDMA)
      3. 4.7.3 Peripheral DMA (PDMA)
         1. 4.7.3.1 PDMA Unsupported Features
         2. 4.7.3.2 Module Allocations
         3. 4.7.3.3 Resets, Interrupts, and Clocks
      4. 4.7.4 Packet DMA (PKTDMA)
         1. 4.7.4.1 Packet DMA (PKTDMA)
         2. 4.7.4.2 Resets, Interrupts, and Clocks
   8. 4.8  Audio
      1. 4.8.1 Audio Tracking Logic (ATL)
         1. 4.8.1.1 ATL Module Allocations
         2. 4.8.1.2 Resets, Interrupts, and Clocks
      2. 4.8.2 Multichannel Audio Serial Port (MCASP)
         1. 4.8.2.1 MCASP Unsupported Features
         2. 4.8.2.2 Module Allocations
         3. 4.8.2.3 Resets, Interrupts, and Clocks
   9. 4.9  General Connectivity
      1. 4.9.1 General Purpose Input/Output (GPIO)
         1. 4.9.1.1 GPIO Unsupported Features
         2. 4.9.1.2 Module Allocation
         3. 4.9.1.3 Resets, Interrupts, and Clocks
      2. 4.9.2 Inter-Integrated Circiuit (I2C)
         1. 4.9.2.1 I2C Unsupported Features
         2. 4.9.2.2 Module Allocations
         3. 4.9.2.3 Resets, Interrupts, and Clocks
      3. 4.9.3 Multichannel Serial Peripheral Interface (MCSPI)
         1. 4.9.3.1 MCSPI SPI Unsupported Features
         2. 4.9.3.2 Module Allocations
         3. 4.9.3.3 Resets, Interrupts, and Clocks
      4. 4.9.4 Universal Asynchronous Receiver/Transmitter (UART)
         1. 4.9.4.1 UART Unsupported Features
         2. 4.9.4.2 Module Allocations
         3. 4.9.4.3 Resets, Interrupts, and Clocks
   10. 4.10 High-speed Serial Interfaces
       1. 4.10.1 Peripheral Component Interconnect Express (PCIe) Subsystem
          1. 4.10.1.1 Module Allocations
          2. 4.10.1.2 Resets, Interrupts, and Clocks
       2. 4.10.2 Gigabit Ethernet Switch (CPSW)
          1. 4.10.2.1 CPSW Unsupported Features
          2. 4.10.2.2 Module Allocations
          3. 4.10.2.3 Resets, Interrupts, and Clocks
       3. 4.10.3 Serializer/Deserializer (SerDes)
          1. 4.10.3.1 Module Allocations
          2. 4.10.3.2 Resets, Interrupts, and Clocks
       4. 4.10.4 Universal Serial Bus Subsystem (USB)
          1. 4.10.4.1 USB2SS Unsupported Features
          2. 4.10.4.2 Module Allocations
          3. 4.10.4.3 Resets, Interrupts, and Clocks
   11. 4.11 Memory Interfaces
       1. 4.11.1 Flash Subsystem (FSS)
          1. 4.11.1.1 FSS Unsupported Features
          2. 4.11.1.2 Module Allocations
          3. 4.11.1.3 Resets, Interrupts, and Clocks
       2. 4.11.2 Octal Serial Peripheral Interface (OSPI)
          1. 4.11.2.1 OSPI Unsupported Features
          2. 4.11.2.2 Module Allocations
          3. 4.11.2.3 Resets, Interrupts, and Clocks
       3. 4.11.3 General-Purpose Memory Controller (GPMC)
          1. 4.11.3.1 GPMC Unsupported Features
          2. 4.11.3.2 Module Allocations
          3. 4.11.3.3 Resets, Interrupts, and Clocks
       4. 4.11.4 Error Location Module (ELM)
          1. 4.11.4.1 ELM Unsupported Features
          2. 4.11.4.2 Module Allocations
          3. 4.11.4.3 Resets, Interrupts, and Clocks
       5. 4.11.5 Multimedia Card Secure Digital (MMCSD)
          1. 4.11.5.1 MMCSD Unsupported Features
          2. 4.11.5.2 Module Allocations
          3. 4.11.5.3 Resets, Interrupts, and Clocks
   12. 4.12 Industrial and Control Interfaces
       1. 4.12.1 Modular Controller Area Network (MCAN)
          1. 4.12.1.1 MCAN Unsupported Features
          2. 4.12.1.2 Module Allocations
          3. 4.12.1.3 Resets, Interrupts, and Clocks
       2. 4.12.2 Enhanced Capture (ECAP)
          1. 4.12.2.1 ECAP Unsupported Features
          2. 4.12.2.2 Module Allocations
          3. 4.12.2.3 Resets, Interrupts, and Clocks
       3. 4.12.3 Enhanced Pulse Width Modulation (EPWM)
          1. 4.12.3.1 EPWM Unsupported Features
          2. 4.12.3.2 Module Allocations
          3. 4.12.3.3 Resets, Interrupts, and Clocks
       4. 4.12.4 Enhanced Quadrature Encoder Pulse (EQEP)
          1. 4.12.4.1 EQEP Unsupported Features
          2. 4.12.4.2 Module Allocations
          3. 4.12.4.3 Resets, Interrupts, and Clocks
   13. 4.13 Camera Subsystem
       1. 4.13.1 Camera Serial Interface Receiver (CSI_RX_IF)
          1. 4.13.1.1 CSI_RX_IF Unsupported Features
          2. 4.13.1.2 Module Allocations
          3. 4.13.1.3 Resets, Interrupts, and Clocks
       2. 4.13.2 MIPI D-PHY Receiver (DPHY_RX)
          1. 4.13.2.1 DPHY_RX Unsupported Features
          2. 4.13.2.2 Module Allocations
          3. 4.13.2.3 Resets, Interrupts, and Clocks
       3. 4.13.3 MIPI D-PHY Transmitter (DPHY_TX)
          1. 4.13.3.1 DPHY_TX Unsupported Features
          2. 4.13.3.2 Module Allocations
          3. 4.13.3.3 Resets, Interrupts, and Clocks
       4. 4.13.4 Camera Streaming Interface Transmitter (CSI_TX_IF)
          1. 4.13.4.1 Module Allocations
          2. 4.13.4.2 Resets, Interrupts, and Clocks
   14. 4.14 Timer Modules
       1. 4.14.1 Global Timebase Counter (GTC)
          1. 4.14.1.1 GTC Unsupported Features
          2. 4.14.1.2 Module Allocations
          3. 4.14.1.3 Resets, Interrupts, and Clocks
       2. 4.14.2 Real Time Interrupt (RTI)
          1. 4.14.2.1 RTI Unsupported Features
          2. 4.14.2.2 Module Allocations
          3. 4.14.2.3 Resets, Interrupts, and Clocks
       3. 4.14.3 Real-Time Clock (RTC)
          1. 4.14.3.1 RTC Unsupported Features
          2. 4.14.3.2 Module Allocations
          3. 4.14.3.3 Resets, Interrupts, and Clocks
       4. 4.14.4 Timer
          1. 4.14.4.1 Timer Unsupported Features
          2. 4.14.4.2 Module Allocations
          3. 4.14.4.3 Resets, Interrupts, and Clocks
   15. 4.15 Internal Diagnostic Modules
       1. 4.15.1 Dual Clock Comparator (DCC)
          1. 4.15.1.1 DCC Unsupported Features
          2. 4.15.1.2 Module Allocations
          3. 4.15.1.3 Resets, Interrupts, and Clocks
          4. 4.15.1.4 DCC Input Source Clock Mapping
       2. 4.15.2 Error Signaling Module (ESM)
          1. 4.15.2.1 ESM Unsupported Features
          2. 4.15.2.2 Module Allocations
          3. 4.15.2.3 Resets, Interrupts, and Clocks
       3. 4.15.3 Memory Cyclic Redundancy Check (MCRC64)
          1. 4.15.3.1 MCRC64 Unsupported Features
          2. 4.15.3.2 Module Allocations
          3. 4.15.3.3 Resets, Interrupts, and Clocks
       4. 4.15.4 Programmable Built-In Self-Test (PBIST)
          1. 4.15.4.1 Module Allocations
          2. 4.15.4.2 Resets, Interrupts, and Clocks
       5. 4.15.5 ECC Aggregator (ECC_AGGR)
          1. 4.15.5.1 Module Allocations
          2. 4.15.5.2 Resets, Interrupts, and Clocks
   16. 4.16 Display Subsystem (DSS)
       1. 4.16.1 DSS_UL Unsupported Features
       2. 4.16.2 Module Allocations
       3. 4.16.3 Resets, Interrupts, and Clocks
       4. 4.16.4 oldi_tx_core
          1. 4.16.4.1 Module Allocations
          2. 4.16.4.2 Resets, Interrupts, and Clocks
   17. 4.17 On-Chip Debug
       1. 4.17.1 CPT2_PROBE
          1. 4.17.1.1 Module Allocations
          2. 4.17.1.2 Resets, Interrupts, and Clocks
       2. 4.17.2 CTI
          1. 4.17.2.1 Module Allocations
          2. 4.17.2.2 Resets, Interrupts, and Clocks
7. 5 Initialization
   1. 5.1 Initialization Overview
      1. 5.1.1 ROM Code Overview
      2. 5.1.2 Bootloader Modes
      3. 5.1.3 Terminology
   2. 5.2 Boot Process
      1. 5.2.1 Public ROM Code Architecture
         1. 5.2.1.1 Main Module
         2. 5.2.1.2 X509 Module
         3. 5.2.1.3 Buffer Manager Module
         4. 5.2.1.4 Log and Trace Module
         5. 5.2.1.5 System Module
         6. 5.2.1.6 Protocol Module
         7. 5.2.1.7 Driver Module
      2. 5.2.2 M4 ROM Description
      3. 5.2.3 Boot Process Flow
   3. 5.3 Boot Mode Pins
      1. 5.3.1 BOOTMODE Pin Mapping
         1. 5.3.1.1 Primary Boot Mode Selection and Configuration
         2. 5.3.1.2 Backup Boot Mode Selection and Configuration
   4. 5.4 Boot Modes
      1. 5.4.1  OSPI\xSPI\QSPI\SPI Boot
         1. 5.4.1.1 OSPI Boot
            1. 5.4.1.1.1 OSPI Bootloader Operation
               1. 5.4.1.1.1.1 OSPI Initialization Process
               2. 5.4.1.1.1.2 OSPI Loading Process
         2. 5.4.1.2 xSPI Boot
            1. 5.4.1.2.1 xSPI Bootloader Operation
         3. 5.4.1.3 Fast-xSPI Boot Mode Configuration
         4. 5.4.1.4 QSPI Boot
            1. 5.4.1.4.1 QSPI Bootloader Operation
               1. 5.4.1.4.1.1 QSPI Initialization Process
               2. 5.4.1.4.1.2 QSPI Loading Process
         5. 5.4.1.5 SPI Boot
            1. 5.4.1.5.1 SPI Bootloader Operation
               1. 5.4.1.5.1.1 SPI Initialization Process
               2. 5.4.1.5.1.2 SPI Loading Process
      2. 5.4.2  I2C Boot
         1. 5.4.2.1 I2C Bootloader Operation
            1. 5.4.2.1.1 I2C Initialization Process
               1. 5.4.2.1.1.1 Block Size
               2. 5.4.2.1.1.2 Addressing
            2. 5.4.2.1.2 I2C Loading Process
               1. 5.4.2.1.2.1 Loading a Boot Image From EEPROM
      3. 5.4.3  SD Card Boot
         1. 5.4.3.1 SD Card Bootloader Operation
      4. 5.4.4  eMMC Boot
         1. 5.4.4.1 eMMC Bootloader Operation
      5. 5.4.5  Ethernet Boot
         1. 5.4.5.1 Ethernet Bootloader Operation
            1. 5.4.5.1.1 Ethernet Initialization Process
            2. 5.4.5.1.2 Ethernet Loading Process
               1. 5.4.5.1.2.1 Ethernet Boot Data Formats
                  1. 5.4.5.1.2.1.1 Limitations
                  2. 5.4.5.1.2.1.2 BOOTP Request
                     1. 5.4.5.1.2.1.2.1 MAC Header (DIX)
                     2. 5.4.5.1.2.1.2.2 IPv4 Header
                     3. 5.4.5.1.2.1.2.3 UDP Header
                     4. 5.4.5.1.2.1.2.4 BOOTP Payload
                     5. 5.4.5.1.2.1.2.5 TFTP
            3. 5.4.5.1.3 Ethernet Hand Over Process
      6. 5.4.6  USB Boot
         1. 5.4.6.1 USB Bootloader Operation
            1. 5.4.6.1.1 USB-Specific Attributes
               1. 5.4.6.1.1.1 DFU Device Mode
      7. 5.4.7  UART Boot
         1. 5.4.7.1 UART Bootloader Operation
            1. 5.4.7.1.1 Initialization Process
            2. 5.4.7.1.2 UART Loading Process
               1. 5.4.7.1.2.1 UART XMODEM
            3. 5.4.7.1.3 UART Hand-Over Process
      8. 5.4.8  GPMC NOR Boot
         1. 5.4.8.1 GPMC NOR Bootloader Operation
      9. 5.4.9  GPMC NAND Boot
         1. 5.4.9.1 GPMC NAND Bootloader Operation
      10. 5.4.10 Serial NAND Boot
          1. 5.4.10.1 Serial NAND Bootloader Operation
          2. 5.4.10.2 Serial NAND Initialization Process
          3. 5.4.10.3 Serial NAND Loading Process
      11. 5.4.11 No boot/Development boot
   5. 5.5 PLL Configuration
   6. 5.6 Boot Parameter Tables
      1. 5.6.1  Common Header
      2. 5.6.2  PLL Setup
      3. 5.6.3  OSPI/QSPI/SPI Boot Parameter Table
      4. 5.6.4  UART Boot Parameter Table
      5. 5.6.5  I2C Boot Parameter Table
      6. 5.6.6  MMCSD/eMMC Boot Parameter Table
      7. 5.6.7  Ethernet Boot Parameter Table
      8. 5.6.8  xSPI/Fast-xSPI Boot Parameter Table
      9. 5.6.9  USB DFU Boot Parameter Table
      10. 5.6.10 USB MSC Boot Parameter Table
      11. 5.6.11 GPMC NOR Boot Parameter Table
      12. 5.6.12 GPMC NAND Boot Parameter Table
   7. 5.7 Boot Image Format
      1. 5.7.1 Overall Structure
      2. 5.7.2 X.509 Certificate
      3. 5.7.3 Organizational Identifier (OID)
      4. 5.7.4 X.509 Extensions Specific to Boot
         1. 5.7.4.1 Boot Info (OID 1.3.6.1.4.1.294.1.1)
         2. 5.7.4.2 Image Integrity (OID 1.3.6.1.4.1.294.1.2)
      5. 5.7.5 Extended Boot Info Extension
         1. 5.7.5.1 Impact on HS Device
         2. 5.7.5.2 Extended Boot Info Details
         3. 5.7.5.3 Certificate / Component Types
         4. 5.7.5.4 Extended Boot Encryption Info
         5. 5.7.5.5 Component Ordering
         6. 5.7.5.6 Memory Load Sections Overlap with Executable Components
         7. 5.7.5.7 Device Type and Extended Boot Extension
      6. 5.7.6 Generating X.509 Certificates
         1. 5.7.6.1 Key Generation
            1. 5.7.6.1.1 Degenerate RSA Keys
         2. 5.7.6.2 Configuration Script
         3. 5.7.6.3 Image Data
   8. 5.8 Boot Memory Maps
      1. 5.8.1 Memory Layout/MPU
      2. 5.8.2 Global Memory Addresses Used by ROM Code
8. 6 Device Configuration
   1. 6.1 Control Module
   2. 6.2 Power
   3. 6.3 Reset
   4. 6.4 Clocking
9. 7 Processors and Accelerators
   1. 7.1 Arm Cortex-A53 Subsystem (A53SS)
      1. 7.1.1 A53SS Overview
         1. 7.1.1.1 A53SS Introduction
         2. 7.1.1.2 A53SS Features
         3.       525
      2. 7.1.2 A53SS Functional Description
         1. 7.1.2.1  A53SS Block Diagram
         2. 7.1.2.2  Arm Cortex-A53 Cluster
         3. 7.1.2.3  A53SS Interfaces and Async Bridges
         4. 7.1.2.4  A53SS Interrupts
            1. 7.1.2.4.1 A53SS Interrupt Inputs
            2. 7.1.2.4.2 A53SS Interrupt Outputs
         5. 7.1.2.5  A53SS Power Management and Clocking
            1. 7.1.2.5.1 A53SS Power Management
            2. 7.1.2.5.2 A53SS Clocking
         6. 7.1.2.6  A53SS Debug
         7. 7.1.2.7  A53SS Global and Debug Timestamps
         8. 7.1.2.8  A53SS Watchdog
         9. 7.1.2.9  A53SS Functional Safety - ECC Error Injection Support
            1. 7.1.2.9.1 A53 ECC Aggregators During Low Power States
            2. 7.1.2.9.2 Auto-initialization of Memories
            3. 7.1.2.9.3 A53 SRAM Safety
            4. 7.1.2.9.4 A53 SRAM ECC Aggregator Configurations
         10. 7.1.2.10 A53SS Boot
         11. 7.1.2.11 A53SS Interprocessor Communication
   2. 7.2 Arm Cortex R5F Subsystem (R5FSS)
      1. 7.2.1 R5FSS Overview
         1. 7.2.1.1 R5FSS Features
         2. 7.2.1.2 R5FSS Not Supported Features
      2. 7.2.2 R5FSS Functional Description
         1. 7.2.2.1  R5FSS Block Diagram
         2. 7.2.2.2  R5FSS Cortex-R5F Core
            1. 7.2.2.2.1 L1 Caches
            2. 7.2.2.2.2 Tightly-Coupled Memories (TCMs)
            3. 7.2.2.2.3 R5FSS Special Signals
         3. 7.2.2.3  R5FSS Interfaces
            1. 7.2.2.3.1 Initiator Interfaces
            2. 7.2.2.3.2 Target Interfaces
         4. 7.2.2.4  R5FSS Power, Clocking and Reset
            1. 7.2.2.4.1 R5FSS Power
            2. 7.2.2.4.2 R5FSS Clocking
            3. 7.2.2.4.3 R5FSS Reset
         5. 7.2.2.5  R5FSS Vectored Interrupt Manager (VIM)
            1. 7.2.2.5.1 VIM Overview
            2. 7.2.2.5.2 VIM Interrupt Inputs
            3. 7.2.2.5.3 VIM Interrupt Outputs
            4. 7.2.2.5.4 VIM Interrupt Vector Table (VIM RAM)
            5. 7.2.2.5.5 VIM Interrupt Prioritization
            6. 7.2.2.5.6 VIM ECC Support
            7. 7.2.2.5.7 VIM IDLE State
            8. 7.2.2.5.8 VIM Interrupt Handling
               1. 7.2.2.5.8.1 Servicing IRQ Through Vector Interface
               2. 7.2.2.5.8.2 Servicing IRQ Through MMR Interface
               3. 7.2.2.5.8.3 Servicing IRQ Through MMR Interface (Alternative)
               4. 7.2.2.5.8.4 Servicing FIQ
               5. 7.2.2.5.8.5 Servicing FIQ (Alternative)
         6. 7.2.2.6  R5FSS Region Address Translation (RAT)
         7. 7.2.2.7  R5FSS ECC Support
         8. 7.2.2.8  R5FSS Memory View
         9. 7.2.2.9  R5FSS Interrupts
         10. 7.2.2.10 R5FSS Debug and Trace
         11. 7.2.2.11 R5FSS Boot Options
         12. 7.2.2.12 R5FSS Core Memory ECC Events
   3. 7.3 Cortex R5F Subsystem (R5FSS)
      1. 7.3.1 R5FSS Overview
         1. 7.3.1.1 R5FSS Features
         2.       587
      2. 7.3.2 R5FSS Functional Description
         1. 7.3.2.1  R5FSS Block Diagram
         2. 7.3.2.2  R5FSS Cortex-R5F Core
            1. 7.3.2.2.1 L1 Caches
            2. 7.3.2.2.2 Tightly-Coupled Memories (TCMs)
            3. 7.3.2.2.3 R5FSS Special Signals
         3. 7.3.2.3  R5FSS Interfaces
            1. 7.3.2.3.1 Initiator Interfaces
            2. 7.3.2.3.2 Target Interfaces
         4. 7.3.2.4  R5FSS Power, Clocking and Reset
            1. 7.3.2.4.1 R5FSS Power
            2. 7.3.2.4.2 R5FSS Clocking
            3. 7.3.2.4.3 R5FSS Reset
         5. 7.3.2.5  R5FSS Vectored Interrupt Manager (VIM)
            1. 7.3.2.5.1 VIM Overview
            2. 7.3.2.5.2 VIM Interrupt Inputs
            3. 7.3.2.5.3 VIM Interrupt Outputs
            4. 7.3.2.5.4 VIM Interrupt Vector Table (VIM RAM)
            5. 7.3.2.5.5 VIM Interrupt Prioritization
            6. 7.3.2.5.6 VIM ECC Support
            7. 7.3.2.5.7 VIM IDLE State
            8. 7.3.2.5.8 VIM Interrupt Handling
               1. 7.3.2.5.8.1 Servicing IRQ Through Vector Interface
               2. 7.3.2.5.8.2 Servicing IRQ Through MMR Interface
               3. 7.3.2.5.8.3 Servicing IRQ Through MMR Interface (Alternative)
               4. 7.3.2.5.8.4 Servicing FIQ
               5. 7.3.2.5.8.5 Servicing FIQ (Alternative)
         6. 7.3.2.6  R5FSS Region Address Translation (RAT)
            1. 7.3.2.6.1 WKUP R5FSS Usage
            2. 7.3.2.6.2 RAT Function
            3. 7.3.2.6.3 How to use RAT Block in R5
            4. 7.3.2.6.4 Example of Using RAT to Access Full 36b SoC Memory Map
         7. 7.3.2.7  R5FSS ECC Support
         8. 7.3.2.8  R5FSS Memory View
         9. 7.3.2.9  R5FSS Interrupts
         10. 7.3.2.10 R5FSS Debug and Trace
         11. 7.3.2.11 R5FSS Boot Options
         12. 7.3.2.12 R5FSS Core Memory ECC Events
      3. 7.3.3 Vectored Interrupt Manager (VIM)
         1. 7.3.3.1 VIM Overview
            1. 7.3.3.1.1 VIM Features
            2. 7.3.3.1.2 Unsupported Features
            3.        630
         2. 7.3.3.2 VIM Functional Description
            1. 7.3.3.2.1 Block Diagram
            2. 7.3.3.2.2 Interrupt Inputs
            3. 7.3.3.2.3 Interrupt Outputs
            4. 7.3.3.2.4 Priority Interrupt / Nested Interrupts
            5. 7.3.3.2.5 VIC Port
            6. 7.3.3.2.6 Latency
            7. 7.3.3.2.7 Safety
            8. 7.3.3.2.8 IDLE
         3. 7.3.3.3 Interrupt Conditions
            1. 7.3.3.3.1 CPU Interrupts
            2. 7.3.3.3.2 Interrupt Description
               1. 7.3.3.3.2.1 coreN_IRQn
               2. 7.3.3.3.2.2 coreN_FIQn
            3. 7.3.3.3.3 Interrupt Condition Control
               1. 7.3.3.3.3.1 coreN_IRQn
               2. 7.3.3.3.3.2 coreN_FIQn
            4. 7.3.3.3.4 Interrupt Handling
               1. 7.3.3.3.4.1 IRQ through the Vector Interface
               2. 7.3.3.3.4.2 IRQ through MMR Interface
               3. 7.3.3.3.4.3 IRQ through MMR Interface (Alternative)
               4. 7.3.3.3.4.4 FIQ
               5. 7.3.3.3.4.5 FIQ (Alternative)
         4. 7.3.3.4 Memory Map
         5. 7.3.3.5 Module I/O
            1. 7.3.3.5.1 Clocks, Reset, Emulation
            2. 7.3.3.5.2 VBUSP Target Interface
            3. 7.3.3.5.3 Interrupt Inputs
            4. 7.3.3.5.4 Interrupt Outputs
            5. 7.3.3.5.5 VIC Interfaces
            6. 7.3.3.5.6 Compare Outputs
            7. 7.3.3.5.7 ECC Control and Status Bus
            8. 7.3.3.5.8 DFT
            9. 7.3.3.5.9 RAM GPIO
         6. 7.3.3.6 Programmer's Guide
            1. 7.3.3.6.1 Initialization Sequence
            2. 7.3.3.6.2 DED Behavior
            3. 7.3.3.6.3 Power Up/Down Sequence
   4. 7.4 Device Manager Cortex R5F Subsystem (WKUP_R5FSS)
      1. 7.4.1 WKUP_R5FSS Overview
         1. 7.4.1.1 WKUP_R5FSS Features
         2.       672
      2. 7.4.2 WKUP_R5FSS Functional Description
         1. 7.4.2.1  WKUP_R5FSS Block Diagram
         2. 7.4.2.2  WKUP_R5FSS Cortex-R5F Core
            1. 7.4.2.2.1 L1 Caches
            2. 7.4.2.2.2 Tightly-Coupled Memories (TCMs)
            3. 7.4.2.2.3 WKUP_R5FSS Special Signals
         3. 7.4.2.3  WKUP_R5FSS Interfaces
            1. 7.4.2.3.1 Initiator Interfaces
            2. 7.4.2.3.2 Target Interfaces
         4. 7.4.2.4  WKUP_R5FSS Power, Clocking and Reset
            1. 7.4.2.4.1 WKUP_R5FSS Power
            2. 7.4.2.4.2 WKUP_R5FSS Clocking
            3. 7.4.2.4.3 WKUP_R5FSS Reset
         5. 7.4.2.5  WKUP_R5FSS Vectored Interrupt Manager (VIM)
            1. 7.4.2.5.1 VIM Overview
            2. 7.4.2.5.2 VIM Interrupt Inputs
            3. 7.4.2.5.3 VIM Interrupt Outputs
            4. 7.4.2.5.4 VIM Interrupt Vector Table (VIM RAM)
            5. 7.4.2.5.5 VIM Interrupt Prioritization
            6. 7.4.2.5.6 VIM ECC Support
            7. 7.4.2.5.7 VIM IDLE State
            8. 7.4.2.5.8 VIM Interrupt Handling
               1. 7.4.2.5.8.1 Servicing IRQ Through Vector Interface
               2. 7.4.2.5.8.2 Servicing IRQ Through MMR Interface
               3. 7.4.2.5.8.3 Servicing IRQ Through MMR Interface (Alternative)
               4. 7.4.2.5.8.4 Servicing FIQ
               5. 7.4.2.5.8.5 Servicing FIQ (Alternative)
         6. 7.4.2.6  WKUP_R5FSS Region Address Translation (RAT)
            1. 7.4.2.6.1 WKUP R5FSS Usage
            2. 7.4.2.6.2 RAT Function
            3. 7.4.2.6.3 How to use RAT Block in R5
            4. 7.4.2.6.4 Example of Using RAT to Access Full 36b SoC Memory Map
         7. 7.4.2.7  WKUP_R5FSS ECC Support
         8. 7.4.2.8  WKUP_R5FSS Memory View
         9. 7.4.2.9  WKUP_R5FSS Interrupts
         10. 7.4.2.10 WKUP_R5FSS Debug and Trace
         11. 7.4.2.11 WKUP_R5FSS Boot Options
         12. 7.4.2.12 WKUP_R5FSS Core Memory ECC Events
   5. 7.5 Vectored Interrupt Manager (VIM)
      1. 7.5.1 VIM Overview
         1. 7.5.1.1 VIM Features
         2. 7.5.1.2 Unsupported Features
         3.       715
      2. 7.5.2 VIM Functional Description
         1. 7.5.2.1 Block Diagram
         2. 7.5.2.2 Interrupt Inputs
         3. 7.5.2.3 Interrupt Outputs
         4. 7.5.2.4 Priority Interrupt / Nested Interrupts
         5. 7.5.2.5 VIC Port
         6. 7.5.2.6 Latency
         7. 7.5.2.7 Safety
         8. 7.5.2.8 IDLE
      3. 7.5.3 Interrupt Conditions
         1. 7.5.3.1 CPU Interrupts
         2. 7.5.3.2 Interrupt Description
            1. 7.5.3.2.1 coreN_IRQn
            2. 7.5.3.2.2 coreN_FIQn
         3. 7.5.3.3 Interrupt Condition Control
            1. 7.5.3.3.1 coreN_IRQn
            2. 7.5.3.3.2 coreN_FIQn
         4. 7.5.3.4 Interrupt Handling
            1. 7.5.3.4.1 IRQ through the Vector Interface
            2. 7.5.3.4.2 IRQ through MMR Interface
            3. 7.5.3.4.3 IRQ through MMR Interface (Alternative)
            4. 7.5.3.4.4 FIQ
            5. 7.5.3.4.5 FIQ (Alternative)
      4. 7.5.4 Memory Map
      5. 7.5.5 VIM Registers
         1. 7.5.5.1  Revision Register (Base Address + 0x00)
         2. 7.5.5.2  Info Register (Base Address + 0x04)
         3. 7.5.5.3  Prioritized IRQ (Base Address + 0x08)
         4. 7.5.5.4  Prioritized FIQ (Base Address + 0x0C)
         5. 7.5.5.5  IRQ Group Status (Base Address + 0x10)
         6. 7.5.5.6  FIQ Group Status (Base Address + 0x14)
         7. 7.5.5.7  IRQ Vector Address (Base Address + 0x18)
         8. 7.5.5.8  FIQ Vector Address (Base Address + 0x1C)
         9. 7.5.5.9  Active IRQ (Base Address + 0x20)
         10. 7.5.5.10 Active FIQ (Base Address + 0x24)
         11. 7.5.5.11 IRQ Priority Mask Register (Base Address + 0x28)
         12. 7.5.5.12 FIQ Priority Mask Register (Base Address + 0x2C)
         13. 7.5.5.13 DED Vector Address (Base Address + 0x30)
         14. 7.5.5.14 Group M Interrupt Raw Status/Set Register (Base Address + 0x400 + M*0x20 + 0x00)
         15. 7.5.5.15 Group M Interrupt Enabled Status/Clear Register (Base Address + 0x400 + M*0x20 + 0x04)
         16. 7.5.5.16 Group M Interrupt Enabled Set Register (Base Address + 0x400 + M*0x20 + 0x08)
         17. 7.5.5.17 Group M Interrupt Enabled Clear Register (Base Address + 0x400 + M*0x20 + 0x0C)
         18. 7.5.5.18 Group M Interrupt IRQ Enabled Status/Clear Register (Base Address + 0x400 + M*0x20 + 0x10)
         19. 7.5.5.19 Group M Interrupt FIQ Enabled Status/Clear Register (Base Address + 0x400 + M*0x20 + 0x14)
         20. 7.5.5.20 Group M Interrupt Map Register (Base Address + 0x400 + M*0x20 + 0x18)
         21. 7.5.5.21 Group M Type Map Register (Base Address + 0x400 + M*0x20 + 0x1C)
         22. 7.5.5.22 Interrupt Q Priority Register (Base Address + 0x1000 + Q*0x4)
         23. 7.5.5.23 Interrupt Q Vector Register (Base Address + 0x2000 + Q*0x4)
      6. 7.5.6 Module I/O
         1. 7.5.6.1 Clocks, Reset, Emulation
         2. 7.5.6.2 VBUSP Target Interface
         3. 7.5.6.3 Interrupt Inputs
         4. 7.5.6.4 Interrupt Outputs
         5. 7.5.6.5 VIC Interfaces
         6. 7.5.6.6 Compare Outputs
         7. 7.5.6.7 ECC Control and Status Bus
         8. 7.5.6.8 DFT
         9. 7.5.6.9 RAM GPIO
      7. 7.5.7 Programmer's Guide
         1. 7.5.7.1 Initialization Sequence
         2. 7.5.7.2 DED Behavior
         3. 7.5.7.3 Power Up/Down Sequence
   6. 7.6 Video Encoder/Decoder (VENC/VDEC)
      1. 7.6.1 Introduction
      2. 7.6.2 Features
         1. 7.6.2.1 Performance
         2. 7.6.2.2 Codec Related Features
         3. 7.6.2.3 Non-Codec Related Features
      3. 7.6.3 Block Diagram
   7. 7.7 Vision Pre-processing Accelerator (VPAC)
      1. 7.7.1 VPAC Overview
         1. 7.7.1.1 VPAC Features
      2. 7.7.2 VPAC Subsystem Level
         1. 7.7.2.1 VPAC Subsystem Clocks
         2. 7.7.2.2 VPAC Subsystem Resets
         3. 7.7.2.3 VPAC Subsystem Interrupts
         4. 7.7.2.4 VPAC Subsystem SL2 Memory Infrastructure
         5. 7.7.2.5 VPAC Subsystem DMA Infrastructure
         6. 7.7.2.6 VPAC Subsystem Data Formats Support
         7. 7.7.2.7 VPAC Subsystem Debug Features
         8. 7.7.2.8 VPAC Subsystem Security Features
      3. 7.7.3 VPAC Vision Imaging Subsystem (VISS)
         1. 7.7.3.1 VISS Top Level
            1. 7.7.3.1.1  VISS Features
            2. 7.7.3.1.2  VISS Block Diagram
            3. 7.7.3.1.3  VISS Data Flow within VPAC
               1. 7.7.3.1.3.1 VISS On-the-fly Processing
                  1. 7.7.3.1.3.1.1 Non-WDR or Companded WDR Sensors
               2. 7.7.3.1.3.2 VISS Memory to Memory Image Processing
            4. 7.7.3.1.4  VISS Data Formats Support
            5. 7.7.3.1.5  VISS VPORT Interface
            6. 7.7.3.1.6  VISS Submodule Integration Specifics
               1. 7.7.3.1.6.1 LSE Integration
               2. 7.7.3.1.6.2 PCID
               3. 7.7.3.1.6.3 GLBCE Integration
                  1. 7.7.3.1.6.3.1 GLBCE Startup
                  2. 7.7.3.1.6.3.2 GLBCE Bypass
            7. 7.7.3.1.7  VISS Stall Handling
               1. 7.7.3.1.7.1 Stall Handling for Streaming Mode
            8. 7.7.3.1.8  VISS Interrupts
               1. 7.7.3.1.8.1 Interrupts Merging
               2. 7.7.3.1.8.2 Handling of Configuration Error Interrupts
            9. 7.7.3.1.9  VISS Error Correcting Code (ECC) Support
            10. 7.7.3.1.10 VISS Programmer's Guide
                1. 7.7.3.1.10.1 VISS Initialization Sequence
                2. 7.7.3.1.10.2 VISS Configuration Restrictions
                3. 7.7.3.1.10.3 VISS Real-time Operating Requirements
         2. 7.7.3.2 VISS Load Store Engine (LSE)
         3. 7.7.3.3 VISS RAW Frond-End (RAWFE)
            1. 7.7.3.3.1 RAWFE Overview
               1. 7.7.3.3.1.1 RAWFE Supported Features
            2. 7.7.3.3.2 RAWFE Functional Description
               1. 7.7.3.3.2.1 RAWFE Functional Operation
               2. 7.7.3.3.2.2 RAWFE ECC for RAMs
            3. 7.7.3.3.3 RAWFE Interrupts
               1. 7.7.3.3.3.1 RAWFE CPU Interrupts
               2. 7.7.3.3.3.2 RAWFE Debug Events
            4. 7.7.3.3.4 RAWFE Sub-Modules Details
               1. 7.7.3.3.4.1 RAWFE Decompanding Block
                  1. 7.7.3.3.4.1.1 RAWFE Mask & Shift
                  2. 7.7.3.3.4.1.2 RAWFE Piece Wise Linear Operation
                  3. 7.7.3.3.4.1.3 RAWFE Offset/WB-1 Block
                  4. 7.7.3.3.4.1.4 RAWFE LUT Based compression
               2. 7.7.3.3.4.2 RAWFE WDR Merge Block
                  1. 7.7.3.3.4.2.1 RAWFE WDR Motion Adaptive Merge (MA1 / MA2)
                  2. 7.7.3.3.4.2.2 RAWFE Companding LUT
               3. 7.7.3.3.4.3 RAWFE Defective Pixel Correction (DPC) Block for 2x2 Bayer CFA
                  1. 7.7.3.3.4.3.1 RAWFE LUT Based DPC
                  2. 7.7.3.3.4.3.2 RAWFE On-The-Fly (OTF) DPC
               4. 7.7.3.3.4.4 RAWFE Lens Shading Correction (LSC) and Digital Gain (DG) Block
                  1. 7.7.3.3.4.4.1 RAWFE LSC Features Supported
                  2. 7.7.3.3.4.4.2 RAWFE LSC Image Framing with Respect to Gain Map Samples
               5. 7.7.3.3.4.5 RAWFE Gain & Offset Block
               6. 7.7.3.3.4.6 RAWFE H3A
                  1. 7.7.3.3.4.6.1  RAWFE H3A Overview
                  2. 7.7.3.3.4.6.2  RAWFE H3A Top-Level Block Diagram
                  3. 7.7.3.3.4.6.3  RAWFE H3A Line Framing Logic
                  4. 7.7.3.3.4.6.4  RAWFE H3A Optional Preprocessing
                  5. 7.7.3.3.4.6.5  RAWFE H3A Autofocus Engine
                     1. 7.7.3.3.4.6.5.1 RAWFE H3A Paxel Extraction
                     2. 7.7.3.3.4.6.5.2 RAWFE H3A Horizontal FV Calculator
                     3. 7.7.3.3.4.6.5.3 RAWFE H3A HFV Accumulator
                     4. 7.7.3.3.4.6.5.4 RAWFE H3A VFV Calculator
                     5. 7.7.3.3.4.6.5.5 RAWFE H3A VFV Accumulator
                  6. 7.7.3.3.4.6.6  RAWFE H3A AE/AWB Engine
                     1. 7.7.3.3.4.6.6.1 RAWFE H3A Subsampler
                     2. 7.7.3.3.4.6.6.2 RAWFE H3A Additional Black Row of AE/AWB Windows
                     3. 7.7.3.3.4.6.6.3 RAWFE H3A Saturation Check
                     4. 7.7.3.3.4.6.6.4 RAWFE H3A AE/AWB Accumulators
                  7. 7.7.3.3.4.6.7  RAWFE H3A DMA Interface
                  8. 7.7.3.3.4.6.8  RAWFE H3A Events and Status Checking
                  9. 7.7.3.3.4.6.9  RAWFE H3A Interface Mux
                  10. 7.7.3.3.4.6.10 RAWFE H3A interface to LSE
                  11. 7.7.3.3.4.6.11 RAWFE H3A Erratas
            5. 7.7.3.3.5 RAWFE Programmer’s Guide
               1. 7.7.3.3.5.1 RAWFE Core programming details
               2. 7.7.3.3.5.2 RAWFE Initialization Sequence
               3. 7.7.3.3.5.3 RAWFE Real-time Оperating Requirements
            6. 7.7.3.3.6 Pattern Conversion and IR Demosaicing (PCID) Module
               1. 7.7.3.3.6.1 Overview and Feature List
                  1. 7.7.3.3.6.1.1 PCID Features Supported
                  2. 7.7.3.3.6.1.2 Functional Operation
                  3. 7.7.3.3.6.1.3 Calculation of pixel level IR subtraction factors
         4. 7.7.3.4 VISS Spatial Noise Filter (NSF4V)
            1. 7.7.3.4.1 NSF4V Introduction
               1. 7.7.3.4.1.1 NSF4V Features
               2. 7.7.3.4.1.2 NSF4V Not Supported Features
            2. 7.7.3.4.2 NSF4V Overview
               1. 7.7.3.4.2.1 Decomposition Kernel Representation
            3. 7.7.3.4.3 NSF4V Lens Shading Correction Compensation
            4. 7.7.3.4.4 NSF4V Noise Threshold Adaptation to Local Image Intensity
         5. 7.7.3.5 VISS Global/Local Brightness and Contrast Enhancement (GLBCE) Module
            1. 7.7.3.5.1 GLBCE Overview
            2. 7.7.3.5.2 GLBCE Interface
            3. 7.7.3.5.3 GLBCE Core
               1. 7.7.3.5.3.1 GLBCE Core Key Parameters
               2. 7.7.3.5.3.2 GLBCE Iridix Strength Calculation
               3. 7.7.3.5.3.3 GLBCE Iridix Configuration Registers
                  1. 7.7.3.5.3.3.1  GLBCE Iridix Frame Width
                  2. 7.7.3.5.3.3.2  GLBCE Iridix Frame Height
                  3. 7.7.3.5.3.3.3  GLBCE Iridix Control 0
                  4. 7.7.3.5.3.3.4  GLBCE Iridix Control 1
                  5. 7.7.3.5.3.3.5  GLBCE Iridix Strength
                  6. 7.7.3.5.3.3.6  GLBCE Iridix Variance
                  7. 7.7.3.5.3.3.7  GLBCE Iridix Dither
                  8. 7.7.3.5.3.3.8  GLBCE Iridix Amplification Limit
                  9. 7.7.3.5.3.3.9  GLBCE Iridix Slope Min and Max
                  10. 7.7.3.5.3.3.10 GLBCE Iridix Black Level
                  11. 7.7.3.5.3.3.11 GLBCE Iridix White Level
                  12. 7.7.3.5.3.3.12 GLBCE Iridix Asymmetry Function Look-up-table
                  13. 7.7.3.5.3.3.13 GLBCE Iridix Forward and Reverse Perceptual Functions Look-up-tables
                  14. 7.7.3.5.3.3.14 GLBCE Iridix WDR Look-up-table
            4. 7.7.3.5.4 GLBCE Embedded Memory
            5. 7.7.3.5.5 GLBCE General Processing
            6. 7.7.3.5.6 GLBCE Continuous Frame Processing
            7. 7.7.3.5.7 GLBCE Single Image Processing
         6. 7.7.3.6 VISS Flexible Color Processing (FCP) Module
            1. 7.7.3.6.1 FCP Overview
               1. 7.7.3.6.1.1 FCP Features Supported
            2. 7.7.3.6.2 FCP Functional Description
            3. 7.7.3.6.3 FCP Submodule Details
               1. 7.7.3.6.3.1 Flexible CFA / Demosaicing
                  1. 7.7.3.6.3.1.1 Feature-set
                  2. 7.7.3.6.3.1.2 Block Diagram of Flexible CFA
                     1. 7.7.3.6.3.1.2.1 Gradient/Threshold Calculation
                     2. 7.7.3.6.3.1.2.2 Software Controlled Direction Selection
               2. 7.7.3.6.3.2 Edge Enhancer Module Wrapper (WEE)
                  1. 7.7.3.6.3.2.1 EE - Edge Enhancer Block
               3. 7.7.3.6.3.3 Flexible Color Conversion (CC)
                  1. 7.7.3.6.3.3.1 Interface Mux
                  2. 7.7.3.6.3.3.2 Color Conversion (CCM-1)
                  3. 7.7.3.6.3.3.3 RGB to HSX Conversion
                     1. 7.7.3.6.3.3.3.1 Weighted Average Block
                     2. 7.7.3.6.3.3.3.2 Saturation Block
                     3. 7.7.3.6.3.3.3.3 Division Block
                     4. 7.7.3.6.3.3.3.4 LUT Based 12 to 8 Downsampling
                  4. 7.7.3.6.3.3.4 Histogram
                  5. 7.7.3.6.3.3.5 Contrast Stretch / Gamma
                  6. 7.7.3.6.3.3.6 RGB-YUV Conversion
               4. 7.7.3.6.3.4 444-422/420 Chroma Down-sampler
            4. 7.7.3.6.4 FCP Interrupts
            5. 7.7.3.6.5 FCP Programmer’s Guide
               1. 7.7.3.6.5.1 HWA Core Programming Details
               2. 7.7.3.6.5.2 HWA HTS Programming Details
               3. 7.7.3.6.5.3 HWA Data Transfer Programming Details
               4. 7.7.3.6.5.4 Initialization Sequence
               5. 7.7.3.6.5.5 Real-time Operating Requirements
               6. 7.7.3.6.5.6 Power Up/Down Sequence
         7. 7.7.3.7 VISS Edge Enhancer (EE)
            1. 7.7.3.7.1 Edge Enhancer Introduction
               1. 7.7.3.7.1.1 Edge Enhancer Filter
               2. 7.7.3.7.1.2 Edge Sharpener Filter
               3. 7.7.3.7.1.3 Merge Block
            2. 7.7.3.7.2 Edge Enhancer Programming Model
      4. 7.7.4 VPAC Lens Distortion Correction (LDC) Module
         1. 7.7.4.1 LDC Overview
            1. 7.7.4.1.1 LDC Features
         2. 7.7.4.2 LDC Functional Description
            1. 7.7.4.2.1  LDC Block Diagram
            2. 7.7.4.2.2  LDC Clocks
            3. 7.7.4.2.3  LDC Interrupts
               1. 7.7.4.2.3.1 LDC Interrupt Events Description
                  1. 7.7.4.2.3.1.1 PIX_IBLK_OUTOFBOUND
                  2. 7.7.4.2.3.1.2 MESH_IBLK_OUTOFBOUND
                  3. 7.7.4.2.3.1.3 IFR_OUTOFBOUND
                  4. 7.7.4.2.3.1.4 INT_SZOVF
                  5. 7.7.4.2.3.1.5 VPAC_LDC_FR_DONE_EVT
                  6. 7.7.4.2.3.1.6 VPAC_LDC_SL2_WR_ERR
                  7. 7.7.4.2.3.1.7 PIX_IBLK_MEMOVF
                  8. 7.7.4.2.3.1.8 MESH_IBLK_MEMOVF
                  9. 7.7.4.2.3.1.9 VPAC_LDC_VBUSM_RD_ERR
            4. 7.7.4.2.4  LDC Affine Transform
            5. 7.7.4.2.5  LDC Perspective Transformation
            6. 7.7.4.2.6  LDC Lens Distortion Back Mapping
               1. 7.7.4.2.6.1 LDC Mesh Table Storage Format
            7. 7.7.4.2.7  LDC Pixel Interpolation
            8. 7.7.4.2.8  LDC Buffer Management
               1. 7.7.4.2.8.1 LDC Buffer Management
            9. 7.7.4.2.9  LDC Multi Region with Variable Block size
               1. 7.7.4.2.9.1 LDC Region Skip Feature
               2. 7.7.4.2.9.2 LDC Support for sub-set of 3x3 regions
               3. 7.7.4.2.9.3 LDC Limitations of Multi Region Scheme
               4. 7.7.4.2.9.4 LDC Multi Region Block Constrains
            10. 7.7.4.2.10 LDC Multi-pass Frame processing
            11. 7.7.4.2.11 LDC Input/Output Data Formats
            12. 7.7.4.2.12 LDC YUV422 to YUV420 Conversion
            13. 7.7.4.2.13 LDC SL2 Interface (LSE)
                1. 7.7.4.2.13.1 LDC PSA (Parallel Signature Analysis)
            14. 7.7.4.2.14 LDC LUT Mapped Dual Output
            15. 7.7.4.2.15 LDC Band Width Controller
            16. 7.7.4.2.16 LDC Input Block Fetch Limit
            17. 7.7.4.2.17 LDC HTS Interface
            18. 7.7.4.2.18 LDC VBUSM Read Interface
         3. 7.7.4.3 LDC Programmers Guide
            1. 7.7.4.3.1 LDC Programming Geometric Distortion Mode
            2. 7.7.4.3.2 LDC Programming Rotational Video Stabilization (Affine Transformation)
            3. 7.7.4.3.3 LDC Programming Perspective Transformation
            4. 7.7.4.3.4 LDC Programming LSE
            5. 7.7.4.3.5 LDC Programming Restrictions and Special Cases
      5. 7.7.5 VPAC Multi-Scaler (MSC)
         1. 7.7.5.1 MSC Overview
            1. 7.7.5.1.1 MSC Features
            2. 7.7.5.1.2 MSC Not Supported Features
         2. 7.7.5.2 MSC Functional Description
            1. 7.7.5.2.1 MSC Functional Overview
               1. 7.7.5.2.1.1 MSC Submodule Details
                  1. 7.7.5.2.1.1.1 MSC Load Store Engine (MSC_LSE)
                     1. 7.7.5.2.1.1.1.1 MSC_LSE Overview
                        1. 7.5.2.1.1.1.1.1 MSC_LSE Features
                     2. 7.7.5.2.1.1.1.2 MSC_LSE Internal Data Loopback Channel
                     3. 7.7.5.2.1.1.1.3 MSC_LSE PSA Support
                     4. 7.7.5.2.1.1.1.4 MSC_LSE Feature Detailed Description
                  2. 7.7.5.2.1.1.2 MSC_CORE (HWA Core)
                     1. 7.7.5.2.1.1.2.1 MSC_CORE Overview
                     2. 7.7.5.2.1.1.2.2 Polyphase Filter of Vertical/Horizontal Resizers
                        1. 7.5.2.1.1.2.2.1 Filter Data Path Logic
                        2. 7.5.2.1.1.2.2.2 Filter Parameters
                        3. 7.5.2.1.1.2.2.3 Single-Phase Filter Parameters
                        4. 7.5.2.1.1.2.2.4 Interleaved Mode Handling
                        5. 7.5.2.1.1.2.2.5 Input Skip Line Support
                     3. 7.7.5.2.1.1.2.3 Scaler Filter Thread Mapping
                     4. 7.7.5.2.1.1.2.4 Filter Coefficients
                        1. 7.5.2.1.1.2.4.1 Filter Coefficient Parameter Configuration
                        2. 7.5.2.1.1.2.4.2 3/4/5-Tap Filter Configuration
                     5. 7.7.5.2.1.1.2.5 Input/Output ROI Trimmers
            2. 7.7.5.2.2 Resizer Algorithm Details
               1. 7.7.5.2.2.1 Multiple Scales Generations
               2. 7.7.5.2.2.2 Polyphase Filter
                  1. 7.7.5.2.2.2.1 Interpolation/Resampling
                  2. 7.7.5.2.2.2.2 Phase Calculation and Re-sampler
                  3. 7.7.5.2.2.2.3 Shared Coefficient Buffers
                  4. 7.7.5.2.2.2.4 Border Pixel Padding
               3. 7.7.5.2.2.3 ROI Handling
            3. 7.7.5.2.3 MSC Data Formats Supported
         3. 7.7.5.3 MSC Interrupt Conditions
            1. 7.7.5.3.1 CPU Interrupts
            2. 7.7.5.3.2 Interrupt Event Description
               1. 7.7.5.3.2.1 VPAC_MSC_LSE_FR_DONE_EVT_0/1 Events
               2. 7.7.5.3.2.2 VPAC_MSC_LSE_SL2_RD_ERR Interrupt Event
               3. 7.7.5.3.2.3 VPAC_MSC_LSE_SL2_WR_ERR Interrupt Event
         4. 7.7.5.4 MSC Performance
         5. 7.7.5.5 MSC Clocking
         6. 7.7.5.6 MSC Reset
         7. 7.7.5.7 MSC Programmer’s Guide
            1. 7.7.5.7.1 Programming Model
               1. 7.7.5.7.1.1 MSC Programming Guidelines
               2. 7.7.5.7.1.2 MSC_Core Programming Details
               3. 7.7.5.7.1.3 MSC_LSE Programming Details
                  1. 7.7.5.7.1.3.1 Input Thread Configuration:
                  2. 7.7.5.7.1.3.2 Output Channel Configuration
               4. 7.7.5.7.1.4 MSC HTS Programming Details
               5. 7.7.5.7.1.5 MSC Data Transfer Programming Details
               6. 7.7.5.7.1.6 LSE Interrupt Programming
            2. 7.7.5.7.2 Initialization Sequence
            3. 7.7.5.7.3 Real-Time Operating Requirements
            4. 7.7.5.7.4 Power Up/Down Sequence
   8. 7.8 Depth and Motion Perception Accelerator (DMPAC)
      1. 7.8.1 DMPAC Overview
         1. 7.8.1.1 DMPAC Features
   9. 7.9 Graphics Accelerator (GPU)
      1. 7.9.1 GPU Overview
         1. 7.9.1.1 Features Supported
         2.       1058
         3. 7.9.1.2 Unsupported Features
10. 8 Inter-processor Communication Scheme (IPC)
    1. 8.1 Mailbox
       1. 8.1.1 Mailbox Overview
          1. 8.1.1.1 Mailbox Features
          2.       1064
       2. 8.1.2 Mailbox Functional Description
          1. 8.1.2.1 Mailbox Block Diagram
          2. 8.1.2.2 Mailbox Software Reset
          3. 8.1.2.3 Mailbox Power Management
          4. 8.1.2.4 Mailbox Interrupt Requests
          5. 8.1.2.5 Mailbox Assignment
             1. 8.1.2.5.1 Description
          6. 8.1.2.6 Sending and Receiving Messages
             1. 8.1.2.6.1 Description
          7. 8.1.2.7 Example of Communication
       3. 8.1.3 Mailbox Programming Guide
          1. 8.1.3.1 Mailbox Low-level Programming Models
             1. 8.1.3.1.1 Global Initialization
                1. 8.1.3.1.1.1 Surrounding Modules Global Initialization
                2. 8.1.3.1.1.2 Mailbox Global Initialization
                   1. 8.1.3.1.1.2.1 Main Sequence - Mailbox Global Initialization
             2. 8.1.3.1.2 Mailbox Operational Modes Configuration
                1. 8.1.3.1.2.1 Mailbox Processing modes
                   1. 8.1.3.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
                   2. 8.1.3.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
                   3. 8.1.3.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
                   4. 8.1.3.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
             3. 8.1.3.1.3 Mailbox Events Servicing
                1. 8.1.3.1.3.1 Events Servicing in Sending Mode
                2. 8.1.3.1.3.2 Events Servicing in Receiving Mode
    2. 8.2 Spinlock
       1. 8.2.1 Spinlock Overview
          1.       1092
       2. 8.2.2 Spinlock Functional Description
          1. 8.2.2.1 Spinlock Software Reset
          2. 8.2.2.2 Spinlock Power Management
          3. 8.2.2.3 About Spinlocks
          4. 8.2.2.4 Spinlock Functional Operation
       3. 8.2.3 Spinlock Programming Guide
          1. 8.2.3.1 Spinlock Low-level Programming Models
             1. 8.2.3.1.1 Surrounding Modules Global Initialization
             2. 8.2.3.1.2 Basic Spinlock Operations
                1. 8.2.3.1.2.1 Spinlocks Clearing After a System Bug Recovery
                2. 8.2.3.1.2.2 Take and Release Spinlock
    3. 8.3 Secure Proxy (SEC_PROXY)
11. 9 Memory Controllers
    1. 9.1 DDR Subsystem (DDRSS)
       1. 9.1.1 DDRSS Overview
          1.       1108
       2. 9.1.2 DDRSS Environment
       3. 9.1.3 DDRSS Functional Description
          1. 9.1.3.1  Real Time and Non-Real Time Threads
          2. 9.1.3.2  Class of Service (CoS)
          3. 9.1.3.3  AXI Write Data All-Strobes
          4. 9.1.3.4  Inline ECC for SDRAM Data
             1. 9.1.3.4.1 ECC Cache
             2. 9.1.3.4.2 ECC Cache Flush
             3. 9.1.3.4.3 ECC Statistics
          5. 9.1.3.5  Address Alias Prevention
          6. 9.1.3.6  AXI Bus Timeout
          7. 9.1.3.7  Leaky Bucket Function
          8. 9.1.3.8  Drain Function
          9. 9.1.3.9  DDRSS Interrupts
          10. 9.1.3.10 DDRSS Memory Regions
          11. 9.1.3.11 DDRSS Dynamic Frequency Change Interface
          12. 9.1.3.12 DDR Controller Functional Description
              1. 9.1.3.12.1 DDR PHY Interface (DFI)
              2. 9.1.3.12.2 Command Queue
                 1. 9.1.3.12.2.1 Placement Logic
                 2. 9.1.3.12.2.2 Command Selection Logic
              3. 9.1.3.12.3 Transaction Processing
              4. 9.1.3.12.4 Paging Policy
              5. 9.1.3.12.5 DDR Controller Initialization
12. 10Interrupts
    1. 10.1 Interrupt Architecture
       1. 10.1.1 ESM Connectivity
          1. 10.1.1.1 Using WKUP_ESM to Monitor All Error Events in SoC
          2. 10.1.1.2 Using MAIN_ESM to Monitor All Error Interrupts in SoC
          3. 10.1.1.3 ESM Configuration During Deep Sleep Mode
       2. 10.1.2 PSIL Events
       3. 10.1.3 GPIO Interrupt Handling
       4. 10.1.4 Utilizing Miscellaneous Signals as Interrupt
          1. 10.1.4.1 Aggregated Interrupt from Timeout Gasket
          2. 10.1.4.2 Aggregated DCC Interrupt
          3. 10.1.4.3 Aggregated Access Error Interrupt from CBASS
          4. 10.1.4.4 Access Error to Control Register Block Interrupt Aggregation
    2. 10.2 Interrupt Controllers
       1. 10.2.1 Generic Interrupt Controller (GICSS)
          1. 10.2.1.1 GICSS Overview
             1. 10.2.1.1.1 GICSS Features
             2.        1150
             3. 10.2.1.1.2 Unsupported Features
          2. 10.2.1.2 GICSS Integration
          3. 10.2.1.3 GICSS Functional Description
             1. 10.2.1.3.1 GICSS Block Diagram
             2. 10.2.1.3.2 Arm GIC-500
             3. 10.2.1.3.3 GICSS Interrupt Types
             4. 10.2.1.3.4 GICSS Interfaces
             5. 10.2.1.3.5 GICSS Interrupt Outputs
             6. 10.2.1.3.6 GICSS ECC Support
             7. 10.2.1.3.7 GICSS AXI2VBUSM and VBUSM2AXI Bridges
    3. 10.3 Interrupt Router (INTROUTER)
       1. 10.3.1 INTROUTER Integration
    4. 10.4 Interrupt Sources
       1. 10.4.1  C7X256V0_CLEC_INTERRUPT_MAP
       2. 10.4.2  C7X256V1_CLEC_INTERRUPT_MAP
       3. 10.4.3  COMPUTE_CLUSTER0_INTERRUPT_MAP
       4. 10.4.4  CPSW0_INTERRUPT_MAP
       5. 10.4.5  DMASS0_INTAGGR_0_INTERRUPT_MAP
       6. 10.4.6  EPWM0_INTERRUPT_MAP
       7. 10.4.7  EPWM1_INTERRUPT_MAP
       8. 10.4.8  EPWM2_INTERRUPT_MAP
       9. 10.4.9  ESM0_INTERRUPT_MAP
       10. 10.4.10 GICSS0_INTERRUPT_MAP
       11. 10.4.11 GLUELOGIC_A53_EVENTI_GLUE_INTERRUPT_MAP
       12. 10.4.12 GLUELOGIC_EPWM0_SYNC_MUXGLUE_INTERRUPT_MAP
       13. 10.4.13 GLUELOGIC_GLUE_EXT_INTN_INTERRUPT_MAP
       14. 10.4.14 GLUELOGIC_MAIN_DCC_DONE_GLUE_INTERRUPT_MAP
       15. 10.4.15 GLUELOGIC_MCU_ACCESS_ERR_INTR_GLUE_INTERRUPT_MAP
       16. 10.4.16 GLUELOGIC_MCU_CBASS_INTR_OR_GLUE_INTERRUPT_MAP
       17. 10.4.17 GLUELOGIC_MGASKET_INTR_GLUE_INTERRUPT_MAP
       18. 10.4.18 GLUELOGIC_PWM_TRIP_OR_GLUE_INTERRUPT_MAP
       19. 10.4.19 GLUELOGIC_SGASKET_INTR_GLUE_INTERRUPT_MAP
       20. 10.4.20 GLUELOGIC_SOC_ACCESS_ERR_INTR_GLUE_INTERRUPT_MAP
       21. 10.4.21 GLUELOGIC_SOC_CBASS_ERR_INTR_GLUE_INTERRUPT_MAP
       22. 10.4.22 GLUELOGIC_WKUP_PBIST_CPUINTR_INTERRUPT_MAP
       23. 10.4.23 GLUELOGICN_LBIST_DONE_GLUE_INTERRUPT_MAP
       24. 10.4.24 GLUELOGICN_MAIN_PBIST_CPU_GLUE_INTERRUPT_MAP
       25. 10.4.25 HSM0_INTERRUPT_MAP
       26. 10.4.26 MAIN_GPIOMUX_INTROUTER0_INTERRUPT_MAP
       27. 10.4.27 MCU_R5FSS0_CORE0_INTERRUPT_MAP
       28. 10.4.28 PCIE0_INTERRUPT_MAP
       29. 10.4.29 PDMA0_INTERRUPT_MAP
       30. 10.4.30 PDMA1_INTERRUPT_MAP
       31. 10.4.31 PDMA2_INTERRUPT_MAP
       32. 10.4.32 PDMA3_INTERRUPT_MAP
       33. 10.4.33 PINFUNCTION_CP_GEMAC_CPTS0_TS_COMPOUT_INTERRUPT_MAP
       34. 10.4.34 PINFUNCTION_CP_GEMAC_CPTS0_TS_SYNCOUT_INTERRUPT_MAP
       35. 10.4.35 PINFUNCTION_SYNC0_OUTOUT_INTERRUPT_MAP
       36. 10.4.36 PINFUNCTION_SYNC1_OUTOUT_INTERRUPT_MAP
       37. 10.4.37 PINFUNCTION_SYNC2_OUTOUT_INTERRUPT_MAP
       38. 10.4.38 PINFUNCTION_SYNC3_OUTOUT_INTERRUPT_MAP
       39. 10.4.39 R5FSS0_CORE0_INTERRUPT_MAP
       40. 10.4.40 SMS0_COMMON_0_INTERRUPT_MAP
       41. 10.4.41 TIFS0_INTERRUPT_MAP
       42. 10.4.42 TIMESYNC_EVENT_INTROUTER0_INTERRUPT_MAP
       43. 10.4.43 USB0_INTERRUPT_MAP
       44. 10.4.44 WKUP_DEEPSLEEP_SOURCES0_INTERRUPT_MAP
       45. 10.4.45 WKUP_ESM0_INTERRUPT_MAP
       46. 10.4.46 WKUP_MCU_GPIOMUX_INTROUTER0_INTERRUPT_MAP
       47. 10.4.47 WKUP_R5FSS0_CORE0_INTERRUPT_MAP
13. 11Data Movement Architecture
    1. 11.1 Data Movement Architecture Overview
       1. 11.1.1 Overview
          1. 11.1.1.1 Ring Accelerator (RINGACC)
          2. 11.1.1.2 Secure Proxy (SEC_PROXY)
          3. 11.1.1.3 Interrupt Aggregator (INTAGGR)
          4. 11.1.1.4 Packet DMA (PKTDMA)
             1. 11.1.1.4.1 PKTDMA Submodule Descriptions
                1. 11.1.1.4.1.1  Bus Interface Unit
                2. 11.1.1.4.1.2  Config CR
                3. 11.1.1.4.1.3  Configuration Registers
                   1. 11.1.1.4.1.3.1 RX State Mapping
                   2. 11.1.1.4.1.3.2 TX State Mapping
                4. 11.1.1.4.1.4  Tx Packet DMA Unit
                5. 11.1.1.4.1.5  Tx Packet Coherency Unit
                6. 11.1.1.4.1.6  Tx Per Channel Buffers
                7. 11.1.1.4.1.7  Rx Per Channel Buffers
                8. 11.1.1.4.1.8  Rx Packet DMA Unit
                9. 11.1.1.4.1.9  Rx Packet Coherency Unit
                10. 11.1.1.4.1.10 Event Handler
             2. 11.1.1.4.2 Channel Classes
          5. 11.1.1.5 Block Copy DMA (BCDMA)
             1. 11.1.1.5.1 BCDMA Submodule Descriptions
                1. 11.1.1.5.1.1  Bus Interface Unit
                2. 11.1.1.5.1.2  Config CR
                3. 11.1.1.5.1.3  Configuration Registers
                   1. 11.1.1.5.1.3.1 BCDMA Mapping Table
                4. 11.1.1.5.1.4  Read Unit(s)
                5. 11.1.1.5.1.5  TR Coherency Unit
                6. 11.1.1.5.1.6  Per-Copy-Channel Buffers
                7. 11.1.1.5.1.7  Tx Per-Split-Channel Buffers
                8. 11.1.1.5.1.8  Rx Per-Split-Channel Buffers
                9. 11.1.1.5.1.9  Write Unit(s)
                10. 11.1.1.5.1.10 Event Coherency Unit
                11. 11.1.1.5.1.11 Event Handler
             2. 11.1.1.5.2 Channel Classes
       2. 11.1.2 Definition of Terms
       3. 11.1.3 DMSS Hardware/Software Interface
          1. 11.1.3.1 Data Buffers
          2. 11.1.3.2 Descriptors
             1. 11.1.3.2.1 Host Packet Descriptor
             2. 11.1.3.2.2 Host Buffer Descriptor
             3. 11.1.3.2.3 Transfer Request Descriptor
          3. 11.1.3.3 Transfer Request Record
             1. 11.1.3.3.1 Overview
             2. 11.1.3.3.2 Addressing Algorithm
                1. 11.1.3.3.2.1 Linear Addressing (Forward)
             3. 11.1.3.3.3 Transfer Request Formats
             4. 11.1.3.3.4 Flags Field Definition
                1. 11.1.3.3.4.1 Type: TR Type Field
                2. 11.1.3.3.4.2 EVENT_SIZE: Event Generation Definition
                3. 11.1.3.3.4.3 TRIGGER_INFO: TR Triggers
                4. 11.1.3.3.4.4 TRIGGERX_TYPE: Trigger Type
                5. 11.1.3.3.4.5 TRIGGERX: Trigger Selection
                6. 11.1.3.3.4.6 Configuration Specific Flags Definition
             5. 11.1.3.3.5 TR Address and Size Attributes
                1. 11.1.3.3.5.1  ICNT0
                2. 11.1.3.3.5.2  ICNT1
                3. 11.1.3.3.5.3  ADDR
                4. 11.1.3.3.5.4  DIM1
                5. 11.1.3.3.5.5  ICNT2
                6. 11.1.3.3.5.6  ICNT3
                7. 11.1.3.3.5.7  DIM2
                8. 11.1.3.3.5.8  DIM3
                9. 11.1.3.3.5.9  DDIM1
                10. 11.1.3.3.5.10 DADDR
                11. 11.1.3.3.5.11 DDIM2
                12. 11.1.3.3.5.12 DDIM3
                13. 11.1.3.3.5.13 DICNT0
                14. 11.1.3.3.5.14 DICNT1
                15. 11.1.3.3.5.15 DICNT2
                16. 11.1.3.3.5.16 DICNT3
          4. 11.1.3.4 Transfer Response Record
             1. 11.1.3.4.1 STATUS Field Definition
                1. 11.1.3.4.1.1 STATUS_TYPE Definitions
                   1. 11.1.3.4.1.1.1 Transfer Error
                   2. 11.1.3.4.1.1.2 Aborted Error
                   3. 11.1.3.4.1.1.3 Submission Error
                   4. 11.1.3.4.1.1.4 Unsupported Feature
                   5. 11.1.3.4.1.1.5 Transfer Exception
                   6. 11.1.3.4.1.1.6 Teardown Flush
          5. 11.1.3.5 Channels
          6. 11.1.3.6 Flows
          7. 11.1.3.7 Queues
             1. 11.1.3.7.1 Queue Types
                1. 11.1.3.7.1.1 Transmit Queues
                2. 11.1.3.7.1.2 Transmit Completion Queues
                3. 11.1.3.7.1.3 Free Descriptor / Buffer Queues
                4. 11.1.3.7.1.4 Receive Queues
                5. 11.1.3.7.1.5 Ring Based Queues Implementation
       4. 11.1.4 Operational Description
          1. 11.1.4.1  Resource Allocation
          2. 11.1.4.2  PKTDMA/BCDMA - Ring Operation
             1. 11.1.4.2.1 Queue Initialization
             2. 11.1.4.2.2 Queueing Entries
             3. 11.1.4.2.3 De-queueing Entries
          3. 11.1.4.3  PKTDMA/BCDMA - Output Event Generation
          4. 11.1.4.4  PKTDMA - Transmit Channel Setup
          5. 11.1.4.5  PKTDMA - Transmit Channel Pause
          6. 11.1.4.6  PKTDMA - Transmit Channel Teardown
          7. 11.1.4.7  PKTDMA - Transmit Operation
          8. 11.1.4.8  PKTDMA - Receive Free Descriptor / Buffer Queue Setup
          9. 11.1.4.9  PKTDMA - Receive Channel Setup
          10. 11.1.4.10 PKTDMA - Receive Channel Teardown
          11. 11.1.4.11 PKTDMA - Receive Channel Pause
          12. 11.1.4.12 PKTDMA - Receive Operation
          13. 11.1.4.13 BCDMA - Block Copy Channel Setup
          14. 11.1.4.14 BCDMA - Block Copy Channel Pause
          15. 11.1.4.15 BCDMA - Block Copy Channel Teardown
          16. 11.1.4.16 BCDMA - Block Copy Operation (TR Packet)
          17. 11.1.4.17 BCDMA - Block Copy Error/Exception Handling
              1. 11.1.4.17.1 Null Icnt0 Error
              2. 11.1.4.17.2 Unsupported TR Type
              3. 11.1.4.17.3 Bus Errors
          18. 11.1.4.18 BCDMA - Split Transmit Channel Setup
          19. 11.1.4.19 BCDMA - Split Transmit Operation Pause
          20. 11.1.4.20 BCDMA - Split Transmit Channel Teardown
          21. 11.1.4.21 BCDMA - Split Transmit Operation (TR Packet)
          22. 11.1.4.22 BCDMA - Split Transmit Error / Exception Handling
              1. 11.1.4.22.1 Null Icnt0 Error
              2. 11.1.4.22.2 Unsupported TR Type
              3. 11.1.4.22.3 Bus Errors
          23. 11.1.4.23 BCDMA - Split Receive Channel Setup
          24. 11.1.4.24 BCDMA - Split Receive Channel Pause
          25. 11.1.4.25 BCDMA - Split Receive Channel Teardown
          26. 11.1.4.26 BCDMA - Split Receive Operation (TR Packet)
          27. 11.1.4.27 BCDMA - Split Receive Error / Exception Handling
              1. 11.1.4.27.1 PKTDMA Exception Conditions
                 1. 11.1.4.27.1.1 Descriptor Starvation
                 2. 11.1.4.27.1.2 Protocol Errors
                 3. 11.1.4.27.1.3 Dropped Packets
                 4. 11.1.4.27.1.4 Long Packet
              2. 11.1.4.27.2 BCDMA Exception Conditions
                 1. 11.1.4.27.2.1 Reception of EOL Delimiter
                 2. 11.1.4.27.2.2 EOP Asserted Prematurely (Short Packet)
                 3. 11.1.4.27.2.3 EOP Asserted Late (Long Packets)
                 4. 11.1.4.27.2.4 Descriptor Starvation
    2. 11.2 Data Movement Subsystem (DMSS)
       1. 11.2.1 Data Movement Subsystem (DMSS)
          1. 11.2.1.1 DMSS Overview
          2.       1351
          3. 11.2.1.2 DMSS Functional Description
          4. 11.2.1.3 DMSS Interrupt Configuration
             1. 11.2.1.3.1 DMSS Event and Interrupt Flow
                1. 11.2.1.3.1.1 DMSS Interrupt Description
                2. 11.2.1.3.1.2 DMSS Event Description
       2. 11.2.2 Ring Accelerator (RINGACC)
          1. 11.2.2.1 RINGACC Overview
             1. 11.2.2.1.1 RINGACC Features
             2.        1360
             3. 11.2.2.1.2 RINGACC Parameters
          2. 11.2.2.2 RINGACC Functional Description
             1. 11.2.2.2.1 Block Diagram
                1. 11.2.2.2.1.1  Configuration Registers
                2. 11.2.2.2.1.2  Source Command FIFO
                3. 11.2.2.2.1.3  Source Write Data FIFO
                4. 11.2.2.2.1.4  Source Read Data FIFO
                5. 11.2.2.2.1.5  Source Write Status FIFO
                6. 11.2.2.2.1.6  Main State Machine
                7. 11.2.2.2.1.7  Destination Command FIFO
                8. 11.2.2.2.1.8  Destination Write Data FIFO
                9. 11.2.2.2.1.9  Destination Read Data FIFO
                10. 11.2.2.2.1.10 Destination Write Status FIFO
             2. 11.2.2.2.2 RINGACC Functional Operation
                1. 11.2.2.2.2.1 Queue Modes
                   1. 11.2.2.2.2.1.1 Ring Mode
                   2. 11.2.2.2.2.1.2 Messaging Mode
                   3. 11.2.2.2.2.1.3 Credentials Mode
                   4. 11.2.2.2.2.1.4 Peek Support
                   5. 11.2.2.2.2.1.5 Index Register Operation
                2. 11.2.2.2.2.2 VBUSM Target Ring Operations
                3. 11.2.2.2.2.3 VBUSM Initiator Interface Command ID Selection
                4. 11.2.2.2.2.4 Ring Push Operation (VBUSM Write to Source Interface)
                5. 11.2.2.2.2.5 Ring Pop Operation (VBUSM Read from Source Interface)
                6. 11.2.2.2.2.6 Host Doorbell Access
                7. 11.2.2.2.2.7 Queue Push Operation (VBUSM Write to Source Interface)
                8. 11.2.2.2.2.8 Queue Pop Operation (VBUSM Read from Source Interface)
                9. 11.2.2.2.2.9 Mismatched Element Size Handling
             3. 11.2.2.2.3 Events
             4. 11.2.2.2.4 Bus Error Handling
             5. 11.2.2.2.5 Monitors
                1. 11.2.2.2.5.1 Threshold Monitor
                2. 11.2.2.2.5.2 Watermark Monitor
                3. 11.2.2.2.5.3 Starvation Monitor
                4. 11.2.2.2.5.4 Statistics Monitor
                5. 11.2.2.2.5.5 Overflow
                6. 11.2.2.2.5.6 Ring Update Port
                7. 11.2.2.2.5.7 Tracing
       3. 11.2.3 Secure Proxy (SEC_PROXY)
          1. 11.2.3.1 Secure Proxy Overview
             1. 11.2.3.1.1 Secure Proxy Features
             2. 11.2.3.1.2 Secure Proxy Parameters
             3.        1403
          2. 11.2.3.2 Secure Proxy Functional Description
             1. 11.2.3.2.1  Targets
                1. 11.2.3.2.1.1 Ring Accelerator
             2. 11.2.3.2.2  Buffers
             3. 11.2.3.2.3  Proxy Credits
             4. 11.2.3.2.4  Proxy Private Word
             5. 11.2.3.2.5  Completion Byte
             6. 11.2.3.2.6  Proxy Thread Sizes
             7. 11.2.3.2.7  Proxy Thread Interleaving
             8. 11.2.3.2.8  Proxy States
             9. 11.2.3.2.9  Proxy Host Access
             10. 11.2.3.2.10 Proxy Host Writes
             11. 11.2.3.2.11 Proxy Host Reads
             12. 11.2.3.2.12 Buffer Accesses
             13. 11.2.3.2.13 Target Access
             14. 11.2.3.2.14 Error State
             15. 11.2.3.2.15 Permission Inheritance
             16. 11.2.3.2.16 Resource Association
             17. 11.2.3.2.17 Direction
             18. 11.2.3.2.18 Threshold Events
             19. 11.2.3.2.19 Error Events
             20. 11.2.3.2.20 Bus Error and Credits
             21. 11.2.3.2.21 Debug
       4. 11.2.4 Interrupt Aggregator (INTAGGR)
          1. 11.2.4.1 INTAGGR Overview
             1. 11.2.4.1.1 INTAGGR Features
             2.        1430
             3. 11.2.4.1.2 INTAGGR Parameters
          2. 11.2.4.2 INTAGGR Functional Description
             1. 11.2.4.2.1 Submodule Descriptions
                1. 11.2.4.2.1.1 Status/Mask Registers
                2. 11.2.4.2.1.2 Interrupt Mapping Block
                3. 11.2.4.2.1.3 Global Event Input (GEVI) Counters
                4. 11.2.4.2.1.4 Local Event Input (LEVI) to Global Event Conversion
                5. 11.2.4.2.1.5 Global Event Multicast
             2. 11.2.4.2.2 General Functionality
                1. 11.2.4.2.2.1 Event to Interrupt Bit Steering
                2. 11.2.4.2.2.2 Interrupt Status
                3. 11.2.4.2.2.3 Interrupt Masked Status
                4. 11.2.4.2.2.4 Enabling/Disabling Individual Interrupt Source Bits
                5. 11.2.4.2.2.5 Global Event Counting
                6. 11.2.4.2.2.6 Local Event to Global Event Conversion
                7. 11.2.4.2.2.7 Global Event Multicast
       5. 11.2.5 Packet Streaming Interface Link (PSI-L)
          1. 11.2.5.1 PSI-L Overview
          2. 11.2.5.2 PSI-L Functional Description
             1. 11.2.5.2.1 PSI-L Introduction
             2. 11.2.5.2.2 PSI-L Operation
             3. 11.2.5.2.3 Event Transport
             4. 11.2.5.2.4 Threads
             5. 11.2.5.2.5 Arbitration Protocol
             6. 11.2.5.2.6 Thread Configuration
                1. 11.2.5.2.6.1 Thread Pairing
                   1. 11.2.5.2.6.1.1 Configuration Transaction Pairing
                2. 11.2.5.2.6.2 Configuration Registers Region
    3. 11.3 Peripheral DMA (PDMA)
       1. 11.3.1 PDMA Controller
          1. 11.3.1.1 PDMA Overview
             1. 11.3.1.1.1 PDMA Features
                1. 11.3.1.1.1.1 PDMA0 - SPI Features
                2. 11.3.1.1.1.2 PDMA1 - UART Features
                3. 11.3.1.1.1.3 PDMA2 - McASP Features
          2.       1466
          3. 11.3.1.2 Functional Description - SPI
             1. 11.3.1.2.1 Compliance to Standards
             2. 11.3.1.2.2 Functional Operation
                1. 11.3.1.2.2.1 Submodule Descriptions
                   1. 11.3.1.2.2.1.1 Scheduler
                   2. 11.3.1.2.2.1.2 Tx Per Channel Buffers
                   3. 11.3.1.2.2.1.3 Tx DMA Unit
                   4. 11.3.1.2.2.1.4 Rx Per Channel Buffers
                   5. 11.3.1.2.2.1.5 Rx DMA Unit
                2. 11.3.1.2.2.2 General Functionality (Applicable to All Functions/Modes)
                   1. 11.3.1.2.2.2.1 Operational States
                   2. 11.3.1.2.2.2.2 Clock Stop
                   3. 11.3.1.2.2.2.3 Emulation Control
                   4. 11.3.1.2.2.2.4 Dynamic Clock Gating
                3. 11.3.1.2.2.3 Events and Flow Control
                   1. 11.3.1.2.2.3.1 Channel Triggering
                   2. 11.3.1.2.2.3.2 Completion Events
                   3. 11.3.1.2.2.3.3 Channel Types
                      1. 11.3.1.2.2.3.3.1 X-Y FIFO Mode
                      2. 11.3.1.2.2.3.3.2 MCAN Mode
                      3. 11.3.1.2.2.3.3.3 AASRC Mode
                4. 11.3.1.2.2.4 Transmit Operation
                   1. 11.3.1.2.2.4.1 Destination (Tx) Channel Allocation
                   2. 11.3.1.2.2.4.2 Destination (Tx) Channel Out of Band Signals
                   3. 11.3.1.2.2.4.3 Destination Channel Initialization
                      1. 11.3.1.2.2.4.3.1 PSI-L Destination Thread Pairing Registers
                         1. 3.1.2.2.4.3.1.1 Enable Register (PSIL Address 0x002)
                         2. 3.1.2.2.4.3.1.2 Local Capabilities Register (PSIL Address 0x040)
                      2. 11.3.1.2.2.4.3.2 PSI-L Destination Thread Pairing
                      3. 11.3.1.2.2.4.3.3 PSI-L Destination Thread Realtime Enable/Count Registers
                         1. 3.1.2.2.4.3.3.1 RT Enable Register (PSIL Address 0x408)
                         2. 3.1.2.2.4.3.3.2 Destination Thread Byte Count Register (PSIL Address 0x404)
                      4. 11.3.1.2.2.4.3.4 Static Transfer Request Setup
                         1. 3.1.2.2.4.3.4.1 X-Y FIFO Mode Static TR
                         2. 3.1.2.2.4.3.4.2 MCAN Mode Static TR
                         3. 3.1.2.2.4.3.4.3 AASRC Mode Static TR
                         4. 3.1.2.2.4.3.4.4 AASRC TxFifoConfig (PSIL Address 0x405)
                         5. 3.1.2.2.4.3.4.5 AASRC TxOrderTable0 (PSIL Address 0x406)
                         6. 3.1.2.2.4.3.4.6 AASRC TxOrderTable1 (PSIL Address 0x407)
                      5. 11.3.1.2.2.4.3.5 PSI-L Destination Thread Enables
                   4. 11.3.1.2.2.4.4 Data Transfer
                      1. 11.3.1.2.2.4.4.1 X-Y FIFO Mode Channel
                         1. 3.1.2.2.4.4.1.1 X-Y FIFO Burst Mode
                      2. 11.3.1.2.2.4.4.2 MCAN Mode Channel
                         1. 3.1.2.2.4.4.2.1 MCAN Burst Mode
                      3. 11.3.1.2.2.4.4.3 AASRC Channel
                   5. 11.3.1.2.2.4.5 Transmit PSI-L Interface Transactions
                   6. 11.3.1.2.2.4.6 Tx Pause
                   7. 11.3.1.2.2.4.7 Tx Teardown
                   8. 11.3.1.2.2.4.8 Tx Channel Reset
                   9. 11.3.1.2.2.4.9 Tx Debug/State Register
                5. 11.3.1.2.2.5 Receive Operation
                   1. 11.3.1.2.2.5.1 Source (Rx) Channel Allocation
                   2. 11.3.1.2.2.5.2 Source Channel Initialization
                      1. 11.3.1.2.2.5.2.1 PSI-L Source Thread Pairing Registers
                         1. 3.1.2.2.5.2.1.1 Peer Thread ID Register (PSIL Address 0x000)
                         2. 3.1.2.2.5.2.1.2 Peer Credit Register (PSIL Address 0x001)
                         3. 3.1.2.2.5.2.1.3 Enable Register (PSIL Address 0x002)
                      2. 11.3.1.2.2.5.2.2 PSI-L Source Thread Realtime Enable/Count Registers
                         1. 3.1.2.2.5.2.2.1 RT Enable Register (PSIL Address 0x408)
                         2. 3.1.2.2.5.2.2.2 Source Thread Byte Count Register (PSIL Address 0x404)
                      3. 11.3.1.2.2.5.2.3 PSI-L Source Thread Pairing
                      4. 11.3.1.2.2.5.2.4 Static Transfer Request Setup
                         1. 3.1.2.2.5.2.4.1 X-Y FIFO Mode Static TR
                         2. 3.1.2.2.5.2.4.2 MCAN Mode Static TR
                         3. 3.1.2.2.5.2.4.3 AASRC Mode Static TR
                         4. 3.1.2.2.5.2.4.4 AASRC RxFifoConfig (PSIL Address 0x405)
                         5. 3.1.2.2.5.2.4.5 AASRC RxOrderTable0 (PSIL Address 0x406)
                         6. 3.1.2.2.5.2.4.6 AASRC RxOrderTable1 (PSIL Address 0x407)
                      5. 11.3.1.2.2.5.2.5 PSI-L Source Thread Enables
                   3. 11.3.1.2.2.5.3 Data Transfer
                      1. 11.3.1.2.2.5.3.1 X-Y FIFO Mode Channel
                         1. 3.1.2.2.5.3.1.1 X-Y FIFO Burst Mode
                      2. 11.3.1.2.2.5.3.2 MCAN Mode Channel
                         1. 3.1.2.2.5.3.2.1 MCAN Burst Mode
                      3. 11.3.1.2.2.5.3.3 AASRC Channel
                   4. 11.3.1.2.2.5.4 Receive PSI-L Interface Transactions
                   5. 11.3.1.2.2.5.5 Rx Pause
                   6. 11.3.1.2.2.5.6 Rx Teardown
                   7. 11.3.1.2.2.5.7 Rx Channel Reset
                   8. 11.3.1.2.2.5.8 Rx Debug/State Register
          4. 11.3.1.3 Functional Description - UART
             1. 11.3.1.3.1 Compliance to Standards
             2. 11.3.1.3.2 Functional Operation
                1. 11.3.1.3.2.1 Submodule Descriptions
                   1. 11.3.1.3.2.1.1 Scheduler
                   2. 11.3.1.3.2.1.2 Tx Per Channel Buffers
                   3. 11.3.1.3.2.1.3 Tx DMA Unit
                   4. 11.3.1.3.2.1.4 Rx Per Channel Buffers
                   5. 11.3.1.3.2.1.5 Rx DMA Unit
                2. 11.3.1.3.2.2 General Functionality (Applicable to All Functions/Modes)
                   1. 11.3.1.3.2.2.1 Operational States
                   2. 11.3.1.3.2.2.2 Clock Stop
                   3. 11.3.1.3.2.2.3 Emulation Control
                   4. 11.3.1.3.2.2.4 Dynamic Clock Gating
                3. 11.3.1.3.2.3 Events and Flow Control
                   1. 11.3.1.3.2.3.1 Channel Triggering
                   2. 11.3.1.3.2.3.2 Completion Events
                   3. 11.3.1.3.2.3.3 Channel Types
                      1. 11.3.1.3.2.3.3.1 X-Y FIFO Mode
                      2. 11.3.1.3.2.3.3.2 MCAN Mode
                      3. 11.3.1.3.2.3.3.3 AASRC Mode
                4. 11.3.1.3.2.4 Transmit Operation
                   1. 11.3.1.3.2.4.1 Destination (Tx) Channel Allocation
                   2. 11.3.1.3.2.4.2 Destination (Tx) Channel Out of Band Signals
                   3. 11.3.1.3.2.4.3 Destination Channel Initialization
                      1. 11.3.1.3.2.4.3.1 PSI-L Destination Thread Pairing Registers
                         1. 3.1.3.2.4.3.1.1 Enable Register (PSIL Address 0x002)
                         2. 3.1.3.2.4.3.1.2 Local Capabilities Register (PSIL Address 0x040)
                      2. 11.3.1.3.2.4.3.2 PSI-L Destination Thread Pairing
                      3. 11.3.1.3.2.4.3.3 PSI-L Destination Thread Realtime Enable/Count Registers
                         1. 3.1.3.2.4.3.3.1 RT Enable Register (PSIL Address 0x408)
                         2. 3.1.3.2.4.3.3.2 Destination Thread Byte Count Register (PSIL Address 0x404)
                      4. 11.3.1.3.2.4.3.4 Static Transfer Request Setup
                         1. 3.1.3.2.4.3.4.1 X-Y FIFO Mode Static TR
                         2. 3.1.3.2.4.3.4.2 MCAN Mode Static TR
                         3. 3.1.3.2.4.3.4.3 AASRC Mode Static TR
                         4. 3.1.3.2.4.3.4.4 AASRC TxFifoConfig (PSIL Address 0x405)
                         5. 3.1.3.2.4.3.4.5 AASRC TxOrderTable0 (PSIL Address 0x406)
                         6. 3.1.3.2.4.3.4.6 AASRC TxOrderTable1 (PSIL Address 0x407)
                      5. 11.3.1.3.2.4.3.5 PSI-L Destination Thread Enables
                   4. 11.3.1.3.2.4.4 Data Transfer
                      1. 11.3.1.3.2.4.4.1 X-Y FIFO Mode Channel
                         1. 3.1.3.2.4.4.1.1 X-Y FIFO Burst Mode
                      2. 11.3.1.3.2.4.4.2 MCAN Mode Channel
                         1. 3.1.3.2.4.4.2.1 MCAN Burst Mode
                      3. 11.3.1.3.2.4.4.3 AASRC Channel
                   5. 11.3.1.3.2.4.5 Transmit PSI-L Interface Transactions
                   6. 11.3.1.3.2.4.6 Tx Pause
                   7. 11.3.1.3.2.4.7 Tx Teardown
                   8. 11.3.1.3.2.4.8 Tx Channel Reset
                   9. 11.3.1.3.2.4.9 Tx Debug/State Register
                5. 11.3.1.3.2.5 Receive Operation
                   1. 11.3.1.3.2.5.1 Source (Rx) Channel Allocation
                   2. 11.3.1.3.2.5.2 Source Channel Initialization
                      1. 11.3.1.3.2.5.2.1 PSI-L Source Thread Pairing Registers
                         1. 3.1.3.2.5.2.1.1 Peer Thread ID Register (PSIL Address 0x000)
                         2. 3.1.3.2.5.2.1.2 Peer Credit Register (PSIL Address 0x001)
                         3. 3.1.3.2.5.2.1.3 Enable Register (PSIL Address 0x002)
                      2. 11.3.1.3.2.5.2.2 PSI-L Source Thread Realtime Enable/Count Registers
                         1. 3.1.3.2.5.2.2.1 RT Enable Register (PSIL Address 0x408)
                         2. 3.1.3.2.5.2.2.2 Source Thread Byte Count Register (PSIL Address 0x404)
                      3. 11.3.1.3.2.5.2.3 PSI-L Source Thread Pairing
                      4. 11.3.1.3.2.5.2.4 Static Transfer Request Setup
                         1. 3.1.3.2.5.2.4.1 X-Y FIFO Mode Static TR
                         2. 3.1.3.2.5.2.4.2 MCAN Mode Static TR
                         3. 3.1.3.2.5.2.4.3 AASRC Mode Static TR
                         4. 3.1.3.2.5.2.4.4 AASRC RxFifoConfig (PSIL Address 0x405)
                         5. 3.1.3.2.5.2.4.5 AASRC RxOrderTable0 (PSIL Address 0x406)
                         6. 3.1.3.2.5.2.4.6 AASRC RxOrderTable1 (PSIL Address 0x407)
                      5. 11.3.1.3.2.5.2.5 PSI-L Source Thread Enables
                   3. 11.3.1.3.2.5.3 Data Transfer
                      1. 11.3.1.3.2.5.3.1 X-Y FIFO Mode Channel
                         1. 3.1.3.2.5.3.1.1 X-Y FIFO Burst Mode
                      2. 11.3.1.3.2.5.3.2 MCAN Mode Channel
                         1. 3.1.3.2.5.3.2.1 MCAN Burst Mode
                      3. 11.3.1.3.2.5.3.3 AASRC Channel
                   4. 11.3.1.3.2.5.4 Receive PSI-L Interface Transactions
                   5. 11.3.1.3.2.5.5 Rx Pause
                   6. 11.3.1.3.2.5.6 Rx Teardown
                   7. 11.3.1.3.2.5.7 Rx Channel Reset
                   8. 11.3.1.3.2.5.8 Rx Debug/State Register
          5. 11.3.1.4 Functional Description - McASP
             1. 11.3.1.4.1 Compliance to Standards
             2. 11.3.1.4.2 Functional Operation
                1. 11.3.1.4.2.1 Submodule Descriptions
                   1. 11.3.1.4.2.1.1 Scheduler
                   2. 11.3.1.4.2.1.2 Tx Per Channel Buffers
                   3. 11.3.1.4.2.1.3 Tx DMA Unit
                   4. 11.3.1.4.2.1.4 Rx Per Channel Buffers
                   5. 11.3.1.4.2.1.5 Rx DMA Unit
                2. 11.3.1.4.2.2 General Functionality (Applicable to All Functions/Modes)
                   1. 11.3.1.4.2.2.1 Operational States
                   2. 11.3.1.4.2.2.2 Clock Stop
                   3. 11.3.1.4.2.2.3 Emulation Control
                3. 11.3.1.4.2.3 Events and Flow Control
                   1. 11.3.1.4.2.3.1 Channel Triggering
                   2. 11.3.1.4.2.3.2 Completion Events
                   3. 11.3.1.4.2.3.3 Channel Types
                      1. 11.3.1.4.2.3.3.1 X-Y FIFO Mode
                      2. 11.3.1.4.2.3.3.2 MCAN Mode
                      3. 11.3.1.4.2.3.3.3 AASRC Mode
                4. 11.3.1.4.2.4 Transmit Operation
                   1. 11.3.1.4.2.4.1 Destination (Tx) Channel Allocation
                   2. 11.3.1.4.2.4.2 Destination (Tx) Channel Out of Band Signals
                   3. 11.3.1.4.2.4.3 Destination Channel Initialization
                      1. 11.3.1.4.2.4.3.1 PSI-L Destination Thread Pairing Registers
                         1. 3.1.4.2.4.3.1.1 Enable Register (PSIL Address 0x002)
                         2. 3.1.4.2.4.3.1.2 Peer Credit Register (PSIL Address 0x040)
                      2. 11.3.1.4.2.4.3.2 PSI-L Destination Thread Pairing
                      3. 11.3.1.4.2.4.3.3 PSI-L Destination Thread Realtime Enable/Count Registers
                         1. 3.1.4.2.4.3.3.1 RT Enable Register (PSIL Address 0x408)
                         2. 3.1.4.2.4.3.3.2 Destination Thread Byte Count Register (PSIL Address 0x404)
                      4. 11.3.1.4.2.4.3.4 Static Transfer Request Setup
                         1. 3.1.4.2.4.3.4.1 X-Y FIFO Mode Static TR
                         2. 3.1.4.2.4.3.4.2 MCAN Mode Static TR
                         3. 3.1.4.2.4.3.4.3 AASRC Mode Static TR
                         4. 3.1.4.2.4.3.4.4 AASRC TxFifoConfig (PSIL Address 0x405)
                         5. 3.1.4.2.4.3.4.5 AASRC TxOrderTable0 (PSIL Address 0x406)
                         6. 3.1.4.2.4.3.4.6 AASRC TxOrderTable1 (PSIL Address 0x407)
                      5. 11.3.1.4.2.4.3.5 PSI-L Destination Thread Enables
                   4. 11.3.1.4.2.4.4 Data Transfer
                      1. 11.3.1.4.2.4.4.1 X-Y FIFO Mode Channel
                         1. 3.1.4.2.4.4.1.1 X-Y FIFO Burst Mode
                      2. 11.3.1.4.2.4.4.2 MCAN Mode Channel
                      3. 11.3.1.4.2.4.4.3 AASRC Channel
                   5. 11.3.1.4.2.4.5 Transmit PSI-L Interface Transactions
                   6. 11.3.1.4.2.4.6 Tx Pause
                   7. 11.3.1.4.2.4.7 Tx Teardown
                   8. 11.3.1.4.2.4.8 Tx Channel Reset
                   9. 11.3.1.4.2.4.9 Tx Debug/State Register
                5. 11.3.1.4.2.5 Receive Operation
                   1. 11.3.1.4.2.5.1 Source (Rx) Channel Allocation
                   2. 11.3.1.4.2.5.2 Source Channel Initialization
                      1. 11.3.1.4.2.5.2.1 PSI-L Source Thread Pairing Registers
                         1. 3.1.4.2.5.2.1.1 Peer Thread ID Register (PSIL Address 0x000)
                         2. 3.1.4.2.5.2.1.2 Peer Credit Register (PSIL Address 0x001)
                         3. 3.1.4.2.5.2.1.3 Enable Register (PSIL Address 0x002)
                      2. 11.3.1.4.2.5.2.2 PSI-L Source Thread Realtime Enable/Count Registers
                         1. 3.1.4.2.5.2.2.1 RT Enable Register (PSIL Address 0x408)
                         2. 3.1.4.2.5.2.2.2 Source Thread Byte Count Register (PSIL Address 0x404)
                      3. 11.3.1.4.2.5.2.3 PSI-L Source Thread Pairing
                      4. 11.3.1.4.2.5.2.4 Static Transfer Request Setup
                         1. 3.1.4.2.5.2.4.1 X-Y FIFO Mode Static TR
                         2. 3.1.4.2.5.2.4.2 MCAN Mode Static TR
                         3. 3.1.4.2.5.2.4.3 AASRC Mode Static TR
                         4. 3.1.4.2.5.2.4.4 AASRC RxFifoConfig (PSIL Address 0x405)
                         5. 3.1.4.2.5.2.4.5 AASRC RxOrderTable0 (PSIL Address 0x406)
                         6. 3.1.4.2.5.2.4.6 AASRC RxOrderTable1 (PSIL Address 0x407)
                      5. 11.3.1.4.2.5.2.5 PSI-L Source Thread Enables
                   3. 11.3.1.4.2.5.3 Data Transfer
                      1. 11.3.1.4.2.5.3.1 X-Y FIFO Mode Channel
                         1. 3.1.4.2.5.3.1.1 X-Y FIFO Burst Mode
                      2. 11.3.1.4.2.5.3.2 MCAN Mode Channel
                      3. 11.3.1.4.2.5.3.3 AASRC Channel
                   4. 11.3.1.4.2.5.4 Receive PSI-L Interface Transactions
                   5. 11.3.1.4.2.5.5 Rx Pause
                   6. 11.3.1.4.2.5.6 Rx Teardown
                   7. 11.3.1.4.2.5.7 Rx Channel Reset
                   8. 11.3.1.4.2.5.8 Rx Debug/State Register
14. 12Peripherals
    1. 12.1 General Connectivity Peripherals
       1. 12.1.1 General-Purpose Interface (GPIO)
          1. 12.1.1.1 GPIO Overview
             1. 12.1.1.1.1 GPIO Features
             2. 12.1.1.1.2 Unsupported Features
             3.        1713
          2. 12.1.1.2 GPIO Environment
             1. 12.1.1.2.1 GPIO Interface Signals
          3. 12.1.1.3 Integration
          4. 12.1.1.4 GPIO Functional Description
             1. 12.1.1.4.1 GPIO Block Diagram
             2. 12.1.1.4.2 GPIO Function
             3. 12.1.1.4.3 Interrupt and Event Generation
                1. 12.1.1.4.3.1 Interrupt Enable (per Bank)
                2. 12.1.1.4.3.2 Trigger Configuration (per Bit)
                3. 12.1.1.4.3.3 Interrupt Status and Clear (per Bit)
             4. 12.1.1.4.4 GPIO Interrupt Connectivity
             5. 12.1.1.4.5 Emulation Halt Operation
          5. 12.1.1.5 GPIO Programming Guide
             1. 12.1.1.5.1 GPIO Low-Level Programming Models
                1. 12.1.1.5.1.1 Global Initialization
                   1. 12.1.1.5.1.1.1 Surrounding Modules Global Initialization
                   2. 12.1.1.5.1.1.2 GPIO Module Global Initialization
                2. 12.1.1.5.1.2 GPIO Operational Modes Configuration
                   1. 12.1.1.5.1.2.1 GPIO Read Input Register
                   2. 12.1.1.5.1.2.2 GPIO Set Bit Function
                   3. 12.1.1.5.1.2.3 GPIO Clear Bit Function
       2. 12.1.2 Inter-Integrated Circuit (I2C) Interface
          1. 12.1.2.1 I2C Overview
             1. 12.1.2.1.1 I2C Features
             2. 12.1.2.1.2 Integration
             3. 12.1.2.1.3 Unsupported Features
             4.        1740
          2. 12.1.2.2 I2C Environment
             1. 12.1.2.2.1 I2C Typical Application
                1. 12.1.2.2.1.1 I2C Pins for Typical Connections in I2C Mode
                2. 12.1.2.2.1.2 I2C Interface Typical Connections
                3. 12.1.2.2.1.3 1745
             2. 12.1.2.2.2 I2C Typical Connection Protocol and Data Format
                1. 12.1.2.2.2.1  I2C Serial Data Format
                2. 12.1.2.2.2.2  I2C Data Validity
                3. 12.1.2.2.2.3  I2C Start and Stop Conditions
                4. 12.1.2.2.2.4  I2C Addressing
                   1. 12.1.2.2.2.4.1 Data Transfer Formats in F/S Mode
                   2. 12.1.2.2.2.4.2 Data Transfer Format in HS Mode
                5. 12.1.2.2.2.5  I2C Controller Transmitter
                6. 12.1.2.2.2.6  I2C Controller Receiver
                7. 12.1.2.2.2.7  I2C Target Transmitter
                8. 12.1.2.2.2.8  I2C Target Receiver
                9. 12.1.2.2.2.9  I2C Bus Arbitration
                10. 12.1.2.2.2.10 I2C Clock Generation and Synchronization
          3. 12.1.2.3 I2C Functional Description
             1. 12.1.2.3.1 I2C Block Diagram
             2. 12.1.2.3.2 I2C Clocks
                1. 12.1.2.3.2.1 I2C Clocking
                2. 12.1.2.3.2.2 I2C Automatic Blocking of the I2C Clock Feature
             3. 12.1.2.3.3 I2C Software Reset
             4. 12.1.2.3.4 I2C Power Management
             5. 12.1.2.3.5 I2C Interrupt Requests
             6. 12.1.2.3.6 I2C Programmable Multitarget Channel Feature
             7. 12.1.2.3.7 I2C FIFO Management
                1. 12.1.2.3.7.1 I2C FIFO Interrupt Mode
                2. 12.1.2.3.7.2 I2C FIFO Polling Mode
                3. 12.1.2.3.7.3 I2C Draining Feature
             8. 12.1.2.3.8 I2C Noise Filter
             9. 12.1.2.3.9 I2C System Test Mode
          4. 12.1.2.4 I2C Programming Guide
             1. 12.1.2.4.1 I2C Low-Level Programming Models
                1. 12.1.2.4.1.1 I2C Programming Model
                   1. 12.1.2.4.1.1.1 Main Program
                      1. 12.1.2.4.1.1.1.1 Configure the Module Before Enabling the I2C Controller
                      2. 12.1.2.4.1.1.1.2 Initialize the I2C Controller
                      3. 12.1.2.4.1.1.1.3 Configure Target Address and the Data Control Register
                      4. 12.1.2.4.1.1.1.4 Initiate a Transfer
                      5. 12.1.2.4.1.1.1.5 Receive Data
                      6. 12.1.2.4.1.1.1.6 Transmit Data
                   2. 12.1.2.4.1.1.2 Interrupt Subroutine Sequence
                   3. 12.1.2.4.1.1.3 Programming Flow-Diagrams
       3. 12.1.3 Multichannel Serial Peripheral Interface (MCSPI)
          1. 12.1.3.1 MCSPI Overview
             1. 12.1.3.1.1 MCSPI Features
             2. 12.1.3.1.2 Unsupported Features
             3.        1790
          2. 12.1.3.2 MCSPI Environment
             1. 12.1.3.2.1 Basic MCSPI Pins for Controller Mode
             2. 12.1.3.2.2 Basic MCSPI Pins for Peripheral Mode
             3. 12.1.3.2.3 MCSPI Protocol and Data Format
                1. 12.1.3.2.3.1 Transfer Format
             4. 12.1.3.2.4 MCSPI in Controller Mode
             5. 12.1.3.2.5 MCSPI in Peripheral Mode
          3. 12.1.3.3 Integration
          4. 12.1.3.4 MCSPI Functional Description
             1. 12.1.3.4.1 MCSPI Block Diagram
             2. 12.1.3.4.2 MCSPI Reset
             3. 12.1.3.4.3 MCSPI Controller Mode
                1. 12.1.3.4.3.1 Controller Mode Features
                2. 12.1.3.4.3.2 Controller Transmit-and-Receive Mode (Full Duplex)
                3. 12.1.3.4.3.3 Controller Transmit-Only Mode (Half Duplex)
                4. 12.1.3.4.3.4 Controller Receive-Only Mode (Half Duplex)
                5. 12.1.3.4.3.5 Single-Channel Controller Mode
                   1. 12.1.3.4.3.5.1 Programming Tips When Switching to Another Channel
                   2. 12.1.3.4.3.5.2 Force SPIEN_[n] Mode
                   3. 12.1.3.4.3.5.3 Turbo Mode
                6. 12.1.3.4.3.6 Start-Bit Mode
                7. 12.1.3.4.3.7 Chip-Select Timing Control
                8. 12.1.3.4.3.8 Programmable MCSPI Clock (SPICLK)
                   1. 12.1.3.4.3.8.1 Clock Ratio Granularity
             4. 12.1.3.4.4 MCSPI Peripheral Mode
                1. 12.1.3.4.4.1 Dedicated Resources
                2. 12.1.3.4.4.2 Peripheral Transmit-and-Receive Mode
                3. 12.1.3.4.4.3 Peripheral Transmit-Only Mode
                4. 12.1.3.4.4.4 Peripheral Receive-Only Mode
             5. 12.1.3.4.5 MCSPI 3-Pin or 4-Pin Mode
             6. 12.1.3.4.6 MCSPI FIFO Buffer Management
                1. 12.1.3.4.6.1 Buffer Almost Full
                2. 12.1.3.4.6.2 Buffer Almost Empty
                3. 12.1.3.4.6.3 End of Transfer Management
                4. 12.1.3.4.6.4 Multiple MCSPI Word Access
                5. 12.1.3.4.6.5 First MCSPI Word Delay
             7. 12.1.3.4.7 MCSPI Interrupts
                1. 12.1.3.4.7.1 Interrupt Events in Controller Mode
                   1. 12.1.3.4.7.1.1 TXx_EMPTY
                   2. 12.1.3.4.7.1.2 TXx_UNDERFLOW
                   3. 12.1.3.4.7.1.3 RXx_ FULL
                   4. 12.1.3.4.7.1.4 End Of Word Count
                2. 12.1.3.4.7.2 Interrupt Events in Peripheral Mode
                   1. 12.1.3.4.7.2.1 TXx_EMPTY
                   2. 12.1.3.4.7.2.2 TXx_UNDERFLOW
                   3. 12.1.3.4.7.2.3 RXx_FULL
                   4. 12.1.3.4.7.2.4 RX0_OVERFLOW
                   5. 12.1.3.4.7.2.5 End Of Word Count
                3. 12.1.3.4.7.3 Interrupt-Driven Operation
                4. 12.1.3.4.7.4 Polling
             8. 12.1.3.4.8 MCSPI DMA Requests
             9. 12.1.3.4.9 MCSPI Power Saving Management
                1. 12.1.3.4.9.1 Normal Mode
                2. 12.1.3.4.9.2 Idle Mode
                   1. 12.1.3.4.9.2.1 Force-Idle Mode
          5. 12.1.3.5 MCSPI Programming Guide
             1. 12.1.3.5.1 MCSPI Global Initialization
                1. 12.1.3.5.1.1 Surrounding Modules Global Initialization
                2. 12.1.3.5.1.2 MCSPI Global Initialization
                   1. 12.1.3.5.1.2.1 Main Sequence – MCSPI Global Initialization
             2. 12.1.3.5.2 MCSPI Operational Mode Configuration
                1. 12.1.3.5.2.1 MCSPI Operational Modes
                   1. 12.1.3.5.2.1.1 Common Transfer Sequence
                   2. 12.1.3.5.2.1.2 End of Transfer Sequences
                   3. 12.1.3.5.2.1.3 Transmit-and-Receive (Controller and Peripheral)
                   4. 12.1.3.5.2.1.4 Transmit-Only (Controller and Peripheral)
                      1. 12.1.3.5.2.1.4.1 Based on Interrupt Requests
                      2. 12.1.3.5.2.1.4.2 Based on DMA Write Requests
                   5. 12.1.3.5.2.1.5 Controller Normal Receive-Only
                      1. 12.1.3.5.2.1.5.1 Based on Interrupt Requests
                      2. 12.1.3.5.2.1.5.2 Based on DMA Read Requests
                   6. 12.1.3.5.2.1.6 Controller Turbo Receive-Only
                      1. 12.1.3.5.2.1.6.1 Based on Interrupt Requests
                      2. 12.1.3.5.2.1.6.2 Based on DMA Read Requests
                   7. 12.1.3.5.2.1.7 Peripheral Receive-Only
                   8. 12.1.3.5.2.1.8 Transfer Procedures With FIFO
                      1. 12.1.3.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
                      2. 12.1.3.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
                      3. 12.1.3.5.2.1.8.3 Transmit-and-Receive With Word Count
                      4. 12.1.3.5.2.1.8.4 Transmit-and-Receive Without Word Count
                      5. 12.1.3.5.2.1.8.5 Transmit-Only
                      6. 12.1.3.5.2.1.8.6 Receive-Only With Word Count
                      7. 12.1.3.5.2.1.8.7 Receive-Only Without Word Count
                   9. 12.1.3.5.2.1.9 Common Transfer Procedures Without FIFO – Polling Method
                      1. 12.1.3.5.2.1.9.1 Receive-Only Procedure – Polling Method
                      2. 12.1.3.5.2.1.9.2 Receive-Only Procedure – Interrupt Method
                      3. 12.1.3.5.2.1.9.3 Transmit-Only Procedure – Polling Method
                      4. 12.1.3.5.2.1.9.4 Transmit-and-Receive Procedure – Polling Method
             3. 12.1.3.5.3 Common Transfer Procedures Without FIFO – Polling Method
                1. 12.1.3.5.3.1 Receive-Only Procedure – Polling Method
                2. 12.1.3.5.3.2 Receive-Only Procedure – Interrupt Method
                3. 12.1.3.5.3.3 Transmit-Only Procedure – Polling Method
                4. 12.1.3.5.3.4 Transmit-and-Receive Procedure – Polling Method
       4. 12.1.4 Universal Asynchronous Receiver/Transmitter (UART)
          1. 12.1.4.1 UART Overview
             1. 12.1.4.1.1 UART Features
             2. 12.1.4.1.2 Unsupported Features
             3.        1888
             4. 12.1.4.1.3 IrDA Features
             5. 12.1.4.1.4 CIR Features
          2. 12.1.4.2 UART Environment
             1. 12.1.4.2.1 UART Functional Interfaces
                1. 12.1.4.2.1.1 System Using UART Communication With Hardware Handshake
                2. 12.1.4.2.1.2 UART Interface Description
                3. 12.1.4.2.1.3 UART Protocol and Data Format
             2. 12.1.4.2.2 RS-485 Functional Interfaces
                1. 12.1.4.2.2.1 System Using RS-485 Communication
                2. 12.1.4.2.2.2 RS-485 Interface Description
             3. 12.1.4.2.3 IrDA Functional Interfaces
                1. 12.1.4.2.3.1 System Using IrDA Communication Protocol
                2. 12.1.4.2.3.2 IrDA Interface Description
                3. 12.1.4.2.3.3 IrDA Protocol and Data Format
                   1. 12.1.4.2.3.3.1 SIR Mode
                      1. 12.1.4.2.3.3.1.1 Frame Format
                      2. 12.1.4.2.3.3.1.2 Asynchronous Transparency
                      3. 12.1.4.2.3.3.1.3 Abort Sequence
                      4. 12.1.4.2.3.3.1.4 Pulse Shaping
                      5. 12.1.4.2.3.3.1.5 Encoder
                      6. 12.1.4.2.3.3.1.6 Decoder
                      7. 12.1.4.2.3.3.1.7 IR Address Checking
                   2. 12.1.4.2.3.3.2 SIR Free-Format Mode
                   3. 12.1.4.2.3.3.3 MIR Mode
                      1. 12.1.4.2.3.3.3.1 MIR Encoder/Decoder
                      2. 12.1.4.2.3.3.3.2 SIP Generation
                   4. 12.1.4.2.3.3.4 FIR Mode
             4. 12.1.4.2.4 CIR Functional Interfaces
                1. 12.1.4.2.4.1 System Using CIR Communication Protocol With Remote Control
                2. 12.1.4.2.4.2 CIR Interface Description
                3. 12.1.4.2.4.3 CIR Protocol and Data Format
                   1. 12.1.4.2.4.3.1 Carrier Modulation
                   2. 12.1.4.2.4.3.2 Pulse Duty Cycle
                   3. 12.1.4.2.4.3.3 Consumer IR Encoding/Decoding
          3. 12.1.4.3 Integration
          4. 12.1.4.4 UART Functional Description
             1. 12.1.4.4.1 UART Block Diagram
             2. 12.1.4.4.2 UART Clock Configuration
             3. 12.1.4.4.3 UART Software Reset
                1. 12.1.4.4.3.1 Independent TX/RX
             4. 12.1.4.4.4 UART Power Management
                1. 12.1.4.4.4.1 UART Mode Power Management
                   1. 12.1.4.4.4.1.1 Module Power Saving
                   2. 12.1.4.4.4.1.2 System Power Saving
                2. 12.1.4.4.4.2 IrDA Mode Power Management
                   1. 12.1.4.4.4.2.1 Module Power Saving
                   2. 12.1.4.4.4.2.2 System Power Saving
                3. 12.1.4.4.4.3 CIR Mode Power Management
                   1. 12.1.4.4.4.3.1 Module Power Saving
                   2. 12.1.4.4.4.3.2 System Power Saving
                4. 12.1.4.4.4.4 Local Power Management
             5. 12.1.4.4.5 UART Interrupt Requests
                1. 12.1.4.4.5.1 UART Mode Interrupt Management
                   1. 12.1.4.4.5.1.1 UART Interrupts
                   2. 12.1.4.4.5.1.2 Wake-Up Interrupt
                2. 12.1.4.4.5.2 IrDA Mode Interrupt Management
                   1. 12.1.4.4.5.2.1 IrDA Interrupts
                   2. 12.1.4.4.5.2.2 Wake-Up Interrupts
                3. 12.1.4.4.5.3 CIR Mode Interrupt Management
                   1. 12.1.4.4.5.3.1 CIR Interrupts
                   2. 12.1.4.4.5.3.2 Wake-Up Interrupts
             6. 12.1.4.4.6 UART FIFO Management
                1. 12.1.4.4.6.1 FIFO Trigger
                   1. 12.1.4.4.6.1.1 Transmit FIFO Trigger
                   2. 12.1.4.4.6.1.2 Receive FIFO Trigger
                2. 12.1.4.4.6.2 FIFO Interrupt Mode
                3. 12.1.4.4.6.3 FIFO Polled Mode Operation
                4. 12.1.4.4.6.4 FIFO DMA Mode Operation
                   1. 12.1.4.4.6.4.1 DMA sequence to disable TX DMA
                   2. 12.1.4.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
                   3. 12.1.4.4.6.4.3 DMA Transmission
                   4. 12.1.4.4.6.4.4 DMA Reception
             7. 12.1.4.4.7 UART Mode Selection
                1. 12.1.4.4.7.1 Register Access Modes
                   1. 12.1.4.4.7.1.1 Operational Mode and Configuration Modes
                   2. 12.1.4.4.7.1.2 Register Access Submode
                   3. 12.1.4.4.7.1.3 Registers Available for the Register Access Modes
                2. 12.1.4.4.7.2 UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
                   1. 12.1.4.4.7.2.1 Registers Available for the UART Function
                   2. 12.1.4.4.7.2.2 Registers Available for the IrDA Function
                   3. 12.1.4.4.7.2.3 Registers Available for the CIR Function
             8. 12.1.4.4.8 UART Protocol Formatting
                1. 12.1.4.4.8.1 UART Mode
                   1. 12.1.4.4.8.1.1 UART Clock Generation: Baud Rate Generation
                   2. 12.1.4.4.8.1.2 Choosing the Appropriate Divisor Value
                   3. 12.1.4.4.8.1.3 UART Data Formatting
                      1. 12.1.4.4.8.1.3.1 Frame Formatting
                      2. 12.1.4.4.8.1.3.2 Hardware Flow Control
                      3. 12.1.4.4.8.1.3.3 Software Flow Control
                         1. 1.4.4.8.1.3.3.1 Receive (RX)
                         2. 1.4.4.8.1.3.3.2 Transmit (TX)
                      4. 12.1.4.4.8.1.3.4 Autobauding Modes
                      5. 12.1.4.4.8.1.3.5 Error Detection
                      6. 12.1.4.4.8.1.3.6 Overrun During Receive
                      7. 12.1.4.4.8.1.3.7 Time-Out and Break Conditions
                         1. 1.4.4.8.1.3.7.1 Time-Out Counter
                         2. 1.4.4.8.1.3.7.2 Break Condition
                2. 12.1.4.4.8.2 RS-485 Mode
                   1. 12.1.4.4.8.2.1 RS-485 External Transceiver Direction Control
                3. 12.1.4.4.8.3 IrDA Mode
                   1. 12.1.4.4.8.3.1 IrDA Clock Generation: Baud Generator
                   2. 12.1.4.4.8.3.2 Choosing the Appropriate Divisor Value
                   3. 12.1.4.4.8.3.3 IrDA Data Formatting
                      1. 12.1.4.4.8.3.3.1  IR RX Polarity Control
                      2. 12.1.4.4.8.3.3.2  IrDA Reception Control
                      3. 12.1.4.4.8.3.3.3  IR Address Checking
                      4. 12.1.4.4.8.3.3.4  Frame Closing
                      5. 12.1.4.4.8.3.3.5  Store and Controlled Transmission
                      6. 12.1.4.4.8.3.3.6  Error Detection
                      7. 12.1.4.4.8.3.3.7  Underrun During Transmission
                      8. 12.1.4.4.8.3.3.8  Overrun During Receive
                      9. 12.1.4.4.8.3.3.9  Status FIFO
                      10. 12.1.4.4.8.3.3.10 Multi-drop Parity Mode with Address Match
                      11. 12.1.4.4.8.3.3.11 Time-guard
                   4. 12.1.4.4.8.3.4 SIR Mode Data Formatting
                      1. 12.1.4.4.8.3.4.1 Abort Sequence
                      2. 12.1.4.4.8.3.4.2 Pulse Shaping
                      3. 12.1.4.4.8.3.4.3 SIR Free Format Programming
                   5. 12.1.4.4.8.3.5 MIR and FIR Mode Data Formatting
                4. 12.1.4.4.8.4 CIR Mode
                   1. 12.1.4.4.8.4.1 CIR Mode Clock Generation
                   2. 12.1.4.4.8.4.2 CIR Data Formatting
                      1. 12.1.4.4.8.4.2.1 IR RX Polarity Control
                      2. 12.1.4.4.8.4.2.2 CIR Transmission
                      3. 12.1.4.4.8.4.2.3 CIR Reception
          5. 12.1.4.5 UART Programming Guide
             1. 12.1.4.5.1 UART Global Initialization
                1. 12.1.4.5.1.1 Surrounding Modules Global Initialization
                2. 12.1.4.5.1.2 UART Module Global Initialization
             2. 12.1.4.5.2 UART Mode selection
             3. 12.1.4.5.3 UART Submode selection
             4. 12.1.4.5.4 UART Load FIFO trigger and DMA mode settings
                1. 12.1.4.5.4.1 DMA mode Settings
                2. 12.1.4.5.4.2 FIFO Trigger Settings
             5. 12.1.4.5.5 UART Protocol, Baud rate and interrupt settings
                1. 12.1.4.5.5.1 Baud rate settings
                2. 12.1.4.5.5.2 Interrupt settings
                3. 12.1.4.5.5.3 Protocol settings
                4. 12.1.4.5.5.4 UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
                5. 12.1.4.5.5.5 UART Multi-drop Parity Address Match Mode Configuration
             6. 12.1.4.5.6 UART Hardware and Software Flow Control Configuration
                1. 12.1.4.5.6.1 Hardware Flow Control Configuration
                2. 12.1.4.5.6.2 Software Flow Control Configuration
             7. 12.1.4.5.7 IrDA Programming Model
                1. 12.1.4.5.7.1 SIR mode
                   1. 12.1.4.5.7.1.1 Receive
                   2. 12.1.4.5.7.1.2 Transmit
                2. 12.1.4.5.7.2 MIR mode
                   1. 12.1.4.5.7.2.1 Receive
                   2. 12.1.4.5.7.2.2 Transmit
                3. 12.1.4.5.7.3 FIR mode
                   1. 12.1.4.5.7.3.1 Receive
                   2. 12.1.4.5.7.3.2 Transmit
    2. 12.2 High-speed Serial Interfaces
       1. 12.2.1 Peripheral Component Interconnect Express (PCIe) Subsystem
          1. 12.2.1.1 PCIe Subsystem Overview
             1. 12.2.1.1.1 PCIe Subsystem Features
             2. 12.2.1.1.2 PCIe Subsystem Not Supported Features
          2. 12.2.1.2 PCIe Subsystem Environment
          3. 12.2.1.3 PCIe Subsystem Functional Description
             1. 12.2.1.3.1  PCIe Subsystem Block Diagram
                1. 12.2.1.3.1.1 PCIe PHY Interface
                   1. 12.2.1.3.1.1.1 PCIe Core Module
                2. 12.2.1.3.1.2 Custom Logic
             2. 12.2.1.3.2  PCIe Subsystem Reset Schemes
                1. 12.2.1.3.2.1 PCIe Conventional Reset
                2. 12.2.1.3.2.2 PCIe Function Level Reset
                3. 12.2.1.3.2.3 PCIe Reset Isolation
                   1. 12.2.1.3.2.3.1 Root Complex Reset with Device Not Reset
                   2. 12.2.1.3.2.3.2 Device Reset with Root Complex Not Reset
                   3. 12.2.1.3.2.3.3 End Point Device Reset with Root Complex Not Reset
                   4. 12.2.1.3.2.3.4 Device Reset with End Point Device Not Reset
                4. 12.2.1.3.2.4 PCIe Reset Limitations
                5. 12.2.1.3.2.5 PCIe Reset Requirements
             3. 12.2.1.3.3  PCIe Subsystem Power Management
                1. 12.2.1.3.3.1 CBA Power Management
             4. 12.2.1.3.4  PCIe Subsystem Interrupts
                1. 12.2.1.3.4.1 Interrupts Aggregation
                2. 12.2.1.3.4.2 Interrupt Generation in EP Mode
                   1. 12.2.1.3.4.2.1 Legacy Interrupt Generation in EP Mode
                   2. 12.2.1.3.4.2.2 MSI and MSI-X Interrupt Generation
                3. 12.2.1.3.4.3 Interrupt Reception in EP Mode
                   1. 12.2.1.3.4.3.1 PCIe Core Downstream Interrupts
                   2. 12.2.1.3.4.3.2 PCIe Core Function Level Reset Interrupts
                   3. 12.2.1.3.4.3.3 PCIe Core Power Management Event Interrupts
                   4. 12.2.1.3.4.3.4 PCIe Core Hot Reset Request Interrupt
                   5. 12.2.1.3.4.3.5 PTM Valid Interrupt
                4. 12.2.1.3.4.4 Interrupt Generation in RC Mode
                5. 12.2.1.3.4.5 Interrupt Reception in RC Mode
                   1. 12.2.1.3.4.5.1 PCIe Legacy Interrupt Reception in RC Mode
                   2. 12.2.1.3.4.5.2 MSI/MSI-X Interrupt Reception in RC Mode
                   3. 12.2.1.3.4.5.3 Advanced Error Reporting Interrupt
                6. 12.2.1.3.4.6 Common Interrupt Reception in RC and EP Modes
                   1. 12.2.1.3.4.6.1 PCIe Local Interrupt
                   2. 12.2.1.3.4.6.2 PHY Interrupt
                   3. 12.2.1.3.4.6.3 Link down Interrupt
                   4. 12.2.1.3.4.6.4 Transaction Error Interrupts
                   5. 12.2.1.3.4.6.5 Power Management Event Interrupt
                7. 12.2.1.3.4.7 ECC Aggregator Interrupts
                8. 12.2.1.3.4.8 CPTS Interrupt
             5. 12.2.1.3.5  PCIe Subsystem DMA Support
                1. 12.2.1.3.5.1 PCIe DMA Support in RC Mode
                2. 12.2.1.3.5.2 PCIe DMA Support in EP Mode
             6. 12.2.1.3.6  PCIe Subsystem Transactions
                1. 12.2.1.3.6.1 PCIe Supported Transactions
                2. 12.2.1.3.6.2 PCIe Transaction Limitations
             7. 12.2.1.3.7  PCIe Subsystem Address Translation
                1. 12.2.1.3.7.1 PCIe Inbound Address Translation
                   1. 12.2.1.3.7.1.1 Root Complex Inbound PCIe to AXI Address Translation
                   2. 12.2.1.3.7.1.2 End Point Inbound PCIe to AXI Address Translation
                2. 12.2.1.3.7.2 PCIe Outbound Address Translation
                   1. 12.2.1.3.7.2.1 PCIe Outbound Address Translation Bypass
             8. 12.2.1.3.8  PCIe Subsystem Quality-of-Service (QoS)
             9. 12.2.1.3.9  PCIe Subsystem Precision Time Measurement (PTM)
             10. 12.2.1.3.10 PCIe Subsystem Loopback
                 1. 12.2.1.3.10.1 PCIe Loopback
                    1. 12.2.1.3.10.1.1 PCIe Loopback Initiator Mode
                    2. 12.2.1.3.10.1.2 PCIe Loopback Target Mode
             11. 12.2.1.3.11 PCIe Subsystem Error Handling
             12. 12.2.1.3.12 PCIe Subsystem Internal Diagnostics Features
                 1. 12.2.1.3.12.1 ECC Aggregators
                 2. 12.2.1.3.12.2 RAM ECC Inversion
       2. 12.2.2 Serializer/Deserializer (SerDes)
          1. 12.2.2.1 SerDes Overview
             1. 12.2.2.1.1 SerDes Features
             2. 12.2.2.1.2 Not Supported Features
             3. 12.2.2.1.3 Industry Standards Compatibility
          2. 12.2.2.2 SerDes Environment
             1. 12.2.2.2.1 SerDes I/Os
          3. 12.2.2.3 SerDes Functional Description
             1. 12.2.2.3.1 SerDes Block Diagram
       3. 12.2.3 Universal Serial Bus Subsystem (USBSS)
          1. 12.2.3.1 USB Overview
             1. 12.2.3.1.1 USB Features
             2. 12.2.3.1.2 Unsupported Features
          2. 12.2.3.2 USB Environment
             1. 12.2.3.2.1 USB Pin List
             2. 12.2.3.2.2 Typical Pin Connections of Device
          3. 12.2.3.3 Integration
          4. 12.2.3.4 Use Cases
             1. 12.2.3.4.1 USB Operational Mode Determination
             2. 12.2.3.4.2 VBUS Voltage Sourcing Control
             3. 12.2.3.4.3 VBUS Detection
             4. 12.2.3.4.4 Pull-up/Pull-down Resistors
       4. 12.2.4 Universal Serial Bus Subsystem (USBSS)
          1. 12.2.4.1 USB Overview
             1. 12.2.4.1.1 USB Features
             2. 12.2.4.1.2 USB Not Supported Features
             3. 12.2.4.1.3 USB Terminology
          2. 12.2.4.2 USB Environment
             1. 12.2.4.2.1 USB I/Os
             2. 12.2.4.2.2 USB Subsystem Application
             3. 12.2.4.2.3 VBUS Sense
          3. 12.2.4.3 USB Functional Description
             1. 12.2.4.3.1 USB Controller Reset
             2. 12.2.4.3.2 Overcurrent Detection
             3. 12.2.4.3.3 Top-Level Initialization Sequence
    3. 12.3 Memory Interfaces
       1. 12.3.1 Flash Subsystem (FSS)
          1. 12.3.1.1 FSS Overview
             1. 12.3.1.1.1 FSS Features
             2. 12.3.1.1.2 Unsupported Features
             3.        2151
          2. 12.3.1.2 FSS Environment
             1. 12.3.1.2.1 FSS Typical Application
          3. 12.3.1.3 Integration
          4. 12.3.1.4 FSS Functional Description
             1. 12.3.1.4.1 FSS Block Diagram
             2. 12.3.1.4.2 FSS Regions
                1. 12.3.1.4.2.1 FSS Regions Boot Size Configuration
             3. 12.3.1.4.3 FSS Memory Regions
          5. 12.3.1.5 FSS Programming Guide
             1. 12.3.1.5.1 FSS Initialization Sequence
             2. 12.3.1.5.2 FSS Power Up/Down Sequence
       2. 12.3.2 Octal Serial Peripheral Interface (OSPI)
          1. 12.3.2.1 OSPI Overview
             1. 12.3.2.1.1 OSPI Features
             2. 12.3.2.1.2 Unsupported Features
             3.        2167
          2. 12.3.2.2 OSPI Environment
          3. 12.3.2.3 Integration
          4. 12.3.2.4 OSPI Functional Description
             1. 12.3.2.4.1  OSPI Block Diagram
                1. 12.3.2.4.1.1 Data Target Interface
                2. 12.3.2.4.1.2 Configuration Target Interface
                3. 12.3.2.4.1.3 OSPI Clock Domains
             2. 12.3.2.4.2  OSPI Modes
                1. 12.3.2.4.2.1 Read Data Capture
                   1. 12.3.2.4.2.1.1 Mechanisms of Data Capturing
                   2. 12.3.2.4.2.1.2 Data Capturing Mechanism Using Taps
                   3. 12.3.2.4.2.1.3 Data Capturing Mechanism Using PHY Module
                   4. 12.3.2.4.2.1.4 External Pull Down on DQS
             3. 12.3.2.4.3  OSPI Power Management
             4. 12.3.2.4.4  Auto HW Polling
             5. 12.3.2.4.5  Flash Reset
             6. 12.3.2.4.6  OSPI Memory Regions
             7. 12.3.2.4.7  OSPI Interrupt Requests
             8. 12.3.2.4.8  OSPI Data Interface
                1. 12.3.2.4.8.1 Data Interface Address Remapping
                2. 12.3.2.4.8.2 Write Protection
                3. 12.3.2.4.8.3 Access Forwarding
             9. 12.3.2.4.9  OSPI Direct Access Controller (DAC)
             10. 12.3.2.4.10 OSPI Indirect Access Controller (INDAC)
                 1. 12.3.2.4.10.1 Indirect Read Controller
                    1. 12.3.2.4.10.1.1 Indirect Read Transfer Process
                 2. 12.3.2.4.10.2 Indirect Write Controller
                    1. 12.3.2.4.10.2.1 Indirect Write Transfer Process
                 3. 12.3.2.4.10.3 Indirect Access Queuing
                 4. 12.3.2.4.10.4 Consecutive Writes and Reads Using Indirect Transfers
                 5. 12.3.2.4.10.5 Accessing the SRAM
             11. 12.3.2.4.11 OSPI Software-Triggered Instruction Generator (STIG)
                 1. 12.3.2.4.11.1 Servicing a STIG Request
             12. 12.3.2.4.12 OSPI Arbitration Between Direct / Indirect Access Controller and STIG
             13. 12.3.2.4.13 OSPI Command Translation
             14. 12.3.2.4.14 Selecting the Flash Instruction Type
             15. 12.3.2.4.15 OSPI Data Interface
             16. 12.3.2.4.16 OSPI PHY Module
                 1. 12.3.2.4.16.1 PHY Pipeline Mode
                 2. 12.3.2.4.16.2 Read Data Capturing by the PHY Module
          5. 12.3.2.5 OSPI Programming Guide
             1. 12.3.2.5.1 Configuring the OSPI Controller for Use After Reset
             2. 12.3.2.5.2 Configuring the OSPI Controller for Optimal Use
             3. 12.3.2.5.3 Using the Flash Command Control Register (STIG Operation)
             4. 12.3.2.5.4 Using SPI Legacy Mode
             5. 12.3.2.5.5 Entering XIP Mode from POR
             6. 12.3.2.5.6 Entering XIP Mode Otherwise
             7. 12.3.2.5.7 Exiting XIP Mode
       3. 12.3.3 General-Purpose Memory Controller (GPMC)
          1. 12.3.3.1 GPMC Overview
             1. 12.3.3.1.1 GPMC Features
             2. 12.3.3.1.2 Unsupported Features
             3.        2220
          2. 12.3.3.2 GPMC Environment
             1. 12.3.3.2.1 GPMC Modes
             2. 12.3.3.2.2 GPMC I/O Signals
          3. 12.3.3.3 Integration
          4. 12.3.3.4 GPMC Functional Description
             1. 12.3.3.4.1  GPMC Block Diagram
             2. 12.3.3.4.2  GPMC Clock Configuration
             3. 12.3.3.4.3  GPMC Power Management
             4. 12.3.3.4.4  GPMC Interrupt Requests
             5. 12.3.3.4.5  GPMC Interconnect Port Interface
             6. 12.3.3.4.6  GPMC Address and Data Bus
                1. 12.3.3.4.6.1 GPMC I/O Configuration Setting
             7. 12.3.3.4.7  GPMC Address Decoder and Chip-Select Configuration
                1. 12.3.3.4.7.1 Chip-Select Base Address and Region Size
                2. 12.3.3.4.7.2 Access Protocol
                   1. 12.3.3.4.7.2.1 Supported Devices
                   2. 12.3.3.4.7.2.2 Access Size Adaptation and Device Width
                   3. 12.3.3.4.7.2.3 Address/Data-Multiplexing Interface
                3. 12.3.3.4.7.3 External Signals
                   1. 12.3.3.4.7.3.1 WAIT Pin Monitoring Control
                      1. 12.3.3.4.7.3.1.1 Wait Monitoring During Asynchronous Read Access
                      2. 12.3.3.4.7.3.1.2 Wait Monitoring During Asynchronous Write Access
                      3. 12.3.3.4.7.3.1.3 Wait Monitoring During Synchronous Read Access
                      4. 12.3.3.4.7.3.1.4 Wait Monitoring During Synchronous Write Access
                      5. 12.3.3.4.7.3.1.5 Wait With NAND Device
                      6. 12.3.3.4.7.3.1.6 Idle Cycle Control Between Successive Accesses
                         1. 3.3.4.7.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                         2. 3.3.4.7.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                         3. 3.3.4.7.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
                      7. 12.3.3.4.7.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
                   2. 12.3.3.4.7.3.2 DIR Pin
                   3. 12.3.3.4.7.3.3 Reset
                   4. 12.3.3.4.7.3.4 Write Protect Signal (nWP)
                   5. 12.3.3.4.7.3.5 Byte Enable (nBE1/nBE0)
                4. 12.3.3.4.7.4 Error Handling
             8. 12.3.3.4.8  GPMC Timing Setting
                1. 12.3.3.4.8.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
                2. 12.3.3.4.8.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
                3. 12.3.3.4.8.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
                4. 12.3.3.4.8.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
                5. 12.3.3.4.8.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
                6. 12.3.3.4.8.6  GPMC_CLKOUT
                7. 12.3.3.4.8.7  GPMC Output Clock and Control Signals Setup and Hold
                8. 12.3.3.4.8.8  Access Time (RDACCESSTIME / WRACCESSTIME)
                   1. 12.3.3.4.8.8.1 Access Time on Read Access
                   2. 12.3.3.4.8.8.2 Access Time on Write Access
                9. 12.3.3.4.8.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
                   1. 12.3.3.4.8.9.1 Page Burst Access Time on Read Access
                   2. 12.3.3.4.8.9.2 Page Burst Access Time on Write Access
                10. 12.3.3.4.8.10 Bus Keeping Support
             9. 12.3.3.4.9  GPMC NOR Access Description
                1. 12.3.3.4.9.1 Asynchronous Access Description
                   1. 12.3.3.4.9.1.1 Access on Address/Data Multiplexed Devices
                      1. 12.3.3.4.9.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
                      2. 12.3.3.4.9.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
                      3. 12.3.3.4.9.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
                   2. 12.3.3.4.9.1.2 Access on Address/Address/Data-Multiplexed Devices
                      1. 12.3.3.4.9.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
                      2. 12.3.3.4.9.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
                      3. 12.3.3.4.9.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
                2. 12.3.3.4.9.2 Synchronous Access Description
                   1. 12.3.3.4.9.2.1 Synchronous Single Read
                   2. 12.3.3.4.9.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
                   3. 12.3.3.4.9.2.3 Synchronous Single Write
                   4. 12.3.3.4.9.2.4 Synchronous Multiple (Burst) Write
                3. 12.3.3.4.9.3 Asynchronous and Synchronous Accesses in non-multiplexed Mode
                   1. 12.3.3.4.9.3.1 Asynchronous Single-Read Operation on non-multiplexed Device
                   2. 12.3.3.4.9.3.2 Asynchronous Single-Write Operation on non-multiplexed Device
                   3. 12.3.3.4.9.3.3 Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
                   4. 12.3.3.4.9.3.4 Synchronous Operations on a non-multiplexed Device
                4. 12.3.3.4.9.4 Page and Burst Support
                5. 12.3.3.4.9.5 System Burst vs External Device Burst Support
             10. 12.3.3.4.10 GPMC pSRAM Access Specificities
             11. 12.3.3.4.11 GPMC NAND Access Description
                 1. 12.3.3.4.11.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
                    1. 12.3.3.4.11.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
                    2. 12.3.3.4.11.1.2 NAND Device Command and Address Phase Control
                    3. 12.3.3.4.11.1.3 Command Latch Cycle
                    4. 12.3.3.4.11.1.4 Address Latch Cycle
                    5. 12.3.3.4.11.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
                    6. 12.3.3.4.11.1.6 NAND Device General Chip-Select Timing Control Requirement
                    7. 12.3.3.4.11.1.7 Read and Write Access Size Adaptation
                       1. 12.3.3.4.11.1.7.1 8-Bit-Wide NAND Device
                       2. 12.3.3.4.11.1.7.2 16-Bit-Wide NAND Device
                 2. 12.3.3.4.11.2 NAND Device-Ready Pin
                    1. 12.3.3.4.11.2.1 Ready Pin Monitored by Software Polling
                    2. 12.3.3.4.11.2.2 Ready Pin Monitored by Hardware Interrupt
                 3. 12.3.3.4.11.3 ECC Calculator
                    1. 12.3.3.4.11.3.1 Hamming Code
                       1. 12.3.3.4.11.3.1.1 ECC Result Register and ECC Computation Accumulation Size
                       2. 12.3.3.4.11.3.1.2 ECC Enabling
                       3. 12.3.3.4.11.3.1.3 ECC Computation
                       4. 12.3.3.4.11.3.1.4 ECC Comparison and Correction
                       5. 12.3.3.4.11.3.1.5 ECC Calculation Based on 8-Bit Word
                       6. 12.3.3.4.11.3.1.6 ECC Calculation Based on 16-Bit Word
                    2. 12.3.3.4.11.3.2 BCH Code
                       1. 12.3.3.4.11.3.2.1 Requirements
                       2. 12.3.3.4.11.3.2.2 Memory Mapping of BCH Codeword
                          1. 3.3.4.11.3.2.2.1 Memory Mapping of Data Message
                          2. 3.3.4.11.3.2.2.2 Memory-Mapping of the ECC
                          3. 3.3.4.11.3.2.2.3 Wrapping Modes
                             1. 3.4.11.3.2.2.3.1  Manual Mode (0x0)
                             2. 3.4.11.3.2.2.3.2  Mode 0x1
                             3. 3.4.11.3.2.2.3.3  Mode 0xA (10)
                             4. 3.4.11.3.2.2.3.4  Mode 0x2
                             5. 3.4.11.3.2.2.3.5  Mode 0x3
                             6. 3.4.11.3.2.2.3.6  Mode 0x7
                             7. 3.4.11.3.2.2.3.7  Mode 0x8
                             8. 3.4.11.3.2.2.3.8  Mode 0x4
                             9. 3.4.11.3.2.2.3.9  Mode 0x9
                             10. 3.4.11.3.2.2.3.10 Mode 0x5
                             11. 3.4.11.3.2.2.3.11 Mode 0xB (11)
                             12. 3.4.11.3.2.2.3.12 Mode 0x6
                       3. 12.3.3.4.11.3.2.3 Supported NAND Page Mappings and ECC Schemes
                          1. 3.3.4.11.3.2.3.1 Per-Sector Spare Mappings
                          2. 3.3.4.11.3.2.3.2 Pooled Spare Mapping
                          3. 3.3.4.11.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
                 4. 12.3.3.4.11.4 Prefetch and Write-Posting Engine
                    1. 12.3.3.4.11.4.1 General Facts About the Engine Configuration
                    2. 12.3.3.4.11.4.2 Prefetch Mode
                    3. 12.3.3.4.11.4.3 FIFO Control in Prefetch Mode
                    4. 12.3.3.4.11.4.4 Write-Posting Mode
                    5. 12.3.3.4.11.4.5 FIFO Control in Write-Posting Mode
                    6. 12.3.3.4.11.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
                    7. 12.3.3.4.11.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
             12. 12.3.3.4.12 GPMC Use Cases and Tips
                 1. 12.3.3.4.12.1 How to Set GPMC Timing Parameters for Typical Accesses
                    1. 12.3.3.4.12.1.1 External Memory Attached to the GPMC Module
                    2. 12.3.3.4.12.1.2 Typical GPMC Setup
                       1. 12.3.3.4.12.1.2.1 GPMC Configuration for Synchronous Burst Read Access
                       2. 12.3.3.4.12.1.2.2 GPMC Configuration for Asynchronous Read Access
                       3. 12.3.3.4.12.1.2.3 GPMC Configuration for Asynchronous Single Write Access
                 2. 12.3.3.4.12.2 How to Choose a Suitable Memory to Use With the GPMC
                    1. 12.3.3.4.12.2.1 Supported Memories or Devices
                       1. 12.3.3.4.12.2.1.1 Memory Pin Multiplexing
                       2. 12.3.3.4.12.2.1.2 NAND Interface Protocol
                       3. 12.3.3.4.12.2.1.3 NOR Interface Protocol
                       4. 12.3.3.4.12.2.1.4 Other Technologies
          5. 12.3.3.5 GPMC Basic Programming Model
             1. 12.3.3.5.1 GPMC High-Level Programming Model Overview
             2. 12.3.3.5.2 GPMC Initialization
             3. 12.3.3.5.3 GPMC Configuration in NOR Mode
             4. 12.3.3.5.4 GPMC Configuration in NAND Mode
             5. 12.3.3.5.5 Set Memory Access
             6. 12.3.3.5.6 GPMC Timing Parameters
                1. 12.3.3.5.6.1 GPMC Timing Parameters Formulas
                   1. 12.3.3.5.6.1.1 NAND Flash Interface Timing Parameters Formulas
                   2. 12.3.3.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
                   3. 12.3.3.5.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
       4. 12.3.4 Error Location Module (ELM)
          1. 12.3.4.1 ELM Overview
             1. 12.3.4.1.1 ELM Features
             2. 12.3.4.1.2 Unsupported Features
             3.        2374
          2. 12.3.4.2 Integration
          3. 12.3.4.3 ELM Functional Description
             1. 12.3.4.3.1 ELM Software Reset
             2. 12.3.4.3.2 ELM Power Management
             3. 12.3.4.3.3 ELM Interrupt Requests
             4. 12.3.4.3.4 ELM Processing Initialization
             5. 12.3.4.3.5 ELM Processing Sequence
             6. 12.3.4.3.6 ELM Processing Completion
          4. 12.3.4.4 ELM Basic Programming Model
             1. 12.3.4.4.1 ELM Low-Level Programming Model
                1. 12.3.4.4.1.1 Processing Initialization
                2. 12.3.4.4.1.2 Read Results
                3. 12.3.4.4.1.3 2387
             2. 12.3.4.4.2 Use Case: ELM Used in Continuous Mode
             3. 12.3.4.4.3 Use Case: ELM Used in Page Mode
       5. 12.3.5 Multi-Media Card Secure Digital (MMCSD) Interface
          1. 12.3.5.1 MMCSD Overview
             1. 12.3.5.1.1 MMCSD Features
             2. 12.3.5.1.2 Unsupported Features
             3.        2394
          2. 12.3.5.2 MMCSD Environment
             1. 12.3.5.2.1 MMCSD IO Mulitplexer
             2. 12.3.5.2.2 Protocol and Data Format
                1. 12.3.5.2.2.1 Protocol
                2. 12.3.5.2.2.2 Data Format
                   1. 12.3.5.2.2.2.1 Coding Scheme for Command Token
                   2. 12.3.5.2.2.2.2 Coding Scheme for Response Token
                   3. 12.3.5.2.2.2.3 Coding Scheme for Data Token
          3. 12.3.5.3 Integration
          4. 12.3.5.4 MMCSD Functional Description
             1. 12.3.5.4.1 Block Diagram
             2. 12.3.5.4.2 Interrupt Requests
             3. 12.3.5.4.3 ECC Support
                1. 12.3.5.4.3.1 ECC Aggregator
             4. 12.3.5.4.4 Advanced DMA
          5. 12.3.5.5 MMCSD Programming Guide
             1. 12.3.5.5.1 Sequences
                1. 12.3.5.5.1.1  SD Card Detection
                2. 12.3.5.5.1.2  SD Clock Control
                   1. 12.3.5.5.1.2.1 Internal Clock Setup Sequence
                   2. 12.3.5.5.1.2.2 SD Clock Supply and Stop Sequence
                   3. 12.3.5.5.1.2.3 SD Clock Frequency Change Sequence
                3. 12.3.5.5.1.3  SD Bus Power Control
                4. 12.3.5.5.1.4  Changing Bus Width
                5. 12.3.5.5.1.5  Timeout Setting on DAT Line
                6. 12.3.5.5.1.6  Card Initialization and Identification (for SD I/F)
                   1. 12.3.5.5.1.6.1 Signal Voltage Switch Procedure (for UHS-I)
                7. 12.3.5.5.1.7  SD Transaction Generation
                   1. 12.3.5.5.1.7.1 Transaction Control without Data Transfer Using DAT Line
                      1. 12.3.5.5.1.7.1.1 The Sequence to Issue a SD Command
                      2. 12.3.5.5.1.7.1.2 The Sequence to Finalize a Command
                      3. 12.3.5.5.1.7.1.3 2426
                   2. 12.3.5.5.1.7.2 Transaction Control with Data Transfer Using DAT Line
                      1. 12.3.5.5.1.7.2.1 Not using DMA
                      2. 12.3.5.5.1.7.2.2 Using SDMA
                      3. 12.3.5.5.1.7.2.3 Using ADMA
                8. 12.3.5.5.1.8  Abort Transaction
                   1. 12.3.5.5.1.8.1 Asynchronous Abort
                   2. 12.3.5.5.1.8.2 Synchronous Abort
                9. 12.3.5.5.1.9  Changing Bus Speed Mode
                10. 12.3.5.5.1.10 Error Recovery
                    1. 12.3.5.5.1.10.1 Error Interrupt Recovery
                    2. 12.3.5.5.1.10.2 Auto CMD12 Error Recovery
                11. 12.3.5.5.1.11 Wakeup Control (Optional)
                12. 12.3.5.5.1.12 Suspend/Resume (Optional, Not Supported from Version 4.00)
                    1. 12.3.5.5.1.12.1 Suspend Sequence
                    2. 12.3.5.5.1.12.2 Resume Sequence
                    3. 12.3.5.5.1.12.3 Stop At Block Gap/Continue Timing for Read Transaction
                    4. 12.3.5.5.1.12.4 Stop At Block Gap/Continue Timing for Write Transaction
             2. 12.3.5.5.2 Driver Flow Sequence
                1. 12.3.5.5.2.1 Host Controller Setup and Card Detection
                   1. 12.3.5.5.2.1.1 Host Controller Setup Sequence
                   2. 12.3.5.5.2.1.2 Card Interface Detection Sequence
                2. 12.3.5.5.2.2 Boot Operation
                   1. 12.3.5.5.2.2.1 Normal Boot Operation: (For Legacy eMMC 5.0)
                   2. 12.3.5.5.2.2.2 Alternate Boot Operation (For Legacy eMMC 5.0):
                   3. 12.3.5.5.2.2.3 Boot Code Chunk Read Operation (For Legacy eMMC 5.0):
                3. 12.3.5.5.2.3 Retuning procedure (For Legacy Interface)
                   1. 12.3.5.5.2.3.1 Sampling Clock Tuning
                   2. 12.3.5.5.2.3.2 Tuning Sequence
                   3. 12.3.5.5.2.3.3 Re-Tuning Modes
                4. 12.3.5.5.2.4 Command Queuing Driver Flow Sequence
                   1. 12.3.5.5.2.4.1 Command Queuing Initialization Sequence
                   2. 12.3.5.5.2.4.2 Task Issuance Sequence
                   3. 12.3.5.5.2.4.3 Task Execution and Completion Sequence
                   4. 12.3.5.5.2.4.4 Task Discard and Clear Sequence
                   5. 12.3.5.5.2.4.5 Error Detect and Recovery when CQ is enabled
    4. 12.4 Industrial and Communication Interfaces
       1. 12.4.1 Modular Controller Area Network (MCAN)
          1. 12.4.1.1 MCAN Overview
             1. 12.4.1.1.1 MCAN Features
             2. 12.4.1.1.2 Unsupported Features
             3.        2467
          2. 12.4.1.2 MCAN Environment
             1. 12.4.1.2.1 CAN Network Basics
          3. 12.4.1.3 Integration
          4. 12.4.1.4 MCAN Functional Description
             1. 12.4.1.4.1  Module Clocking Requirements
             2. 12.4.1.4.2  Interrupt and DMA Requests
                1. 12.4.1.4.2.1 Interrupt Requests
                2. 12.4.1.4.2.2 DMA Requests
             3. 12.4.1.4.3  Operating Modes
                1. 12.4.1.4.3.1 Software Initialization
                2. 12.4.1.4.3.2 Normal Operation
                3. 12.4.1.4.3.3 CAN FD Operation
                4. 12.4.1.4.3.4 Transmitter Delay Compensation
                   1. 12.4.1.4.3.4.1 Description
                   2. 12.4.1.4.3.4.2 Transmitter Delay Compensation Measurement
                5. 12.4.1.4.3.5 Restricted Operation Mode
                6. 12.4.1.4.3.6 Bus Monitoring Mode
                7. 12.4.1.4.3.7 Disabled Automatic Retransmission (DAR) Mode
                   1. 12.4.1.4.3.7.1 Frame Transmission in DAR Mode
                8. 12.4.1.4.3.8 Power Down (Sleep Mode)
                   1. 12.4.1.4.3.8.1 External Clock Stop Mode
                   2. 12.4.1.4.3.8.2 Suspend Mode
                   3. 12.4.1.4.3.8.3 Wakeup request
                9. 12.4.1.4.3.9 Test Modes
                   1. 12.4.1.4.3.9.1 Internal Loopback Mode
             4. 12.4.1.4.4  Timestamp Generation
                1. 12.4.1.4.4.1 External Timestamp Counter
             5. 12.4.1.4.5  Timeout Counter
             6. 12.4.1.4.6  ECC Support
                1. 12.4.1.4.6.1 ECC Wrapper
                2. 12.4.1.4.6.2 ECC Aggregator
             7. 12.4.1.4.7  Rx Handling
                1. 12.4.1.4.7.1 Acceptance Filtering
                   1. 12.4.1.4.7.1.1 Range Filter
                   2. 12.4.1.4.7.1.2 Filter for specific IDs
                   3. 12.4.1.4.7.1.3 Classic Bit Mask Filter
                   4. 12.4.1.4.7.1.4 Standard Message ID Filtering
                   5. 12.4.1.4.7.1.5 Extended Message ID Filtering
                2. 12.4.1.4.7.2 Rx FIFOs
                   1. 12.4.1.4.7.2.1 Rx FIFO Blocking Mode
                   2. 12.4.1.4.7.2.2 Rx FIFO Overwrite Mode
                3. 12.4.1.4.7.3 Dedicated Rx Buffers
                   1. 12.4.1.4.7.3.1 Rx Buffer Handling
                4. 12.4.1.4.7.4 Debug on CAN Support
             8. 12.4.1.4.8  Tx Handling
                1. 12.4.1.4.8.1 Transmit Pause
                2. 12.4.1.4.8.2 Dedicated Tx Buffers
                3. 12.4.1.4.8.3 Tx FIFO
                4. 12.4.1.4.8.4 Tx Queue
                5. 12.4.1.4.8.5 Mixed Dedicated Tx Buffers/Tx FIFO
                6. 12.4.1.4.8.6 Mixed Dedicated Tx Buffers/Tx Queue
                7. 12.4.1.4.8.7 Transmit Cancellation
                8. 12.4.1.4.8.8 Tx Event Handling
             9. 12.4.1.4.9  FIFO Acknowledge Handling
             10. 12.4.1.4.10 Message RAM
                 1. 12.4.1.4.10.1 Message RAM Configuration
                 2. 12.4.1.4.10.2 Rx Buffer and FIFO Element
                 3. 12.4.1.4.10.3 Tx Buffer Element
                 4. 12.4.1.4.10.4 Tx Event FIFO Element
                 5. 12.4.1.4.10.5 Standard Message ID Filter Element
                 6. 12.4.1.4.10.6 Extended Message ID Filter Element
       2. 12.4.2 Enhanced Capture (ECAP) Module
          1. 12.4.2.1 ECAP Overview
             1. 12.4.2.1.1 ECAP Features
             2. 12.4.2.1.2 Unsupported Features
             3.        2533
          2. 12.4.2.2 ECAP Environment
             1. 12.4.2.2.1 ECAP I/O Interface
          3. 12.4.2.3 Integration
          4. 12.4.2.4 ECAP Functional Description
             1. 12.4.2.4.1 Capture and APWM Operating Modes
                1. 12.4.2.4.1.1 ECAP Capture Mode Description
                   1. 12.4.2.4.1.1.1 ECAP Event Prescaler
                   2. 12.4.2.4.1.1.2 ECAP Edge Polarity Select and Qualifier
                   3. 12.4.2.4.1.1.3 ECAP Continuous/One-Shot Control
                   4. 12.4.2.4.1.1.4 ECAP 32-Bit Counter and Phase Control
                   5. 12.4.2.4.1.1.5 CAP1-CAP4 Registers
                   6. 12.4.2.4.1.1.6 ECAP Interrupt Control
                   7. 12.4.2.4.1.1.7 ECAP Shadow Load and Lockout Control
                2. 12.4.2.4.1.2 ECAP APWM Mode Operation
             2. 12.4.2.4.2 Summary of ECAP Functional Registers
          5. 12.4.2.5 ECAP Use Cases
             1. 12.4.2.5.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
                1. 12.4.2.5.1.1 Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
             2. 12.4.2.5.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
                1. 12.4.2.5.2.1 Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
             3. 12.4.2.5.3 Time Difference (Delta) Operation Rising Edge Trigger Example
                1. 12.4.2.5.3.1 Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
             4. 12.4.2.5.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
                1. 12.4.2.5.4.1 Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
             5. 12.4.2.5.5 Application of the APWM Mode
                1. 12.4.2.5.5.1 Simple PWM Generation (Independent Channel/s) Example
                   1. 12.4.2.5.5.1.1 Code Snippet for APWM Mode
                2. 12.4.2.5.5.2 Multichannel PWM Generation with Synchronization Example
                   1. 12.4.2.5.5.2.1 Code Snippet for Multichannel PWM Generation with Synchronization
                3. 12.4.2.5.5.3 Multichannel PWM Generation with Phase Control Example
                   1. 12.4.2.5.5.3.1 Code Snippet for Multichannel PWM Generation with Phase Control
       3. 12.4.3 Enhanced Pulse Width Modulation (EPWM) Module
          1. 12.4.3.1 EPWM Overview
             1. 12.4.3.1.1 EPWM Features
             2. 12.4.3.1.2 Unsupported Features
             3.        2569
             4. 12.4.3.1.3 Multiple EPWM Module Details
          2. 12.4.3.2 EPWM Environment
          3. 12.4.3.3 Integration
          4. 12.4.3.4 EPWM Functional Description
             1. 12.4.3.4.1  EPWM Submodule Features
                1. 12.4.3.4.1.1 Constant Definitions Used in the EPWM Code Examples
             2. 12.4.3.4.2  EPWM Time-Base (TB) Submodule
                1. 12.4.3.4.2.1 Overview
                2. 12.4.3.4.2.2 Controlling and Monitoring the EPWM Time-Base Submodule
                3. 12.4.3.4.2.3 Calculating PWM Period and Frequency
                   1. 12.4.3.4.2.3.1 EPWM Time-Base Period Shadow Register
                   2. 12.4.3.4.2.3.2 EPWM Time-Base Counter Synchronization
                4. 12.4.3.4.2.4 Phase Locking the Time-Base Clocks of Multiple EPWM Modules
                5. 12.4.3.4.2.5 EPWM Time-Base Counter Modes and Timing Waveforms
             3. 12.4.3.4.3  EPWM Counter-Compare (CC) Submodule
                1. 12.4.3.4.3.1 Overview
                2. 12.4.3.4.3.2 Controlling and Monitoring the EPWM Counter-Compare Submodule
                3. 12.4.3.4.3.3 Operational Highlights for the EPWM Counter-Compare Submodule
                4. 12.4.3.4.3.4 EPWM Counter-Compare Submodule Timing Waveforms
             4. 12.4.3.4.4  EPWM Action-Qualifier (AQ) Submodule
                1. 12.4.3.4.4.1 Overview
                2. 12.4.3.4.4.2 Controlling and Monitoring the EPWM Action-Qualifier Submodule
                3. 12.4.3.4.4.3 EPWM Action-Qualifier Event Priority
                4. 12.4.3.4.4.4 Waveforms for Common EPWM Configurations
             5. 12.4.3.4.5  EPWM Dead-Band Generator (DB) Submodule
                1. 12.4.3.4.5.1 Overview
                2. 12.4.3.4.5.2 Controlling and Monitoring the EPWM Dead-Band Submodule
                3. 12.4.3.4.5.3 Operational Highlights for the EPWM Dead-Band Generator Submodule
             6. 12.4.3.4.6  EPWM-Chopper (PC) Submodule
                1. 12.4.3.4.6.1 Overview
                2. 12.4.3.4.6.2 2600
                3. 12.4.3.4.6.3 Controlling the EPWM-Chopper Submodule
                4. 12.4.3.4.6.4 Operational Highlights for the EPWM-Chopper Submodule
                5. 12.4.3.4.6.5 EPWM-Chopper Waveforms
                   1. 12.4.3.4.6.5.1 EPWM-Chopper One-Shot Pulse
                   2. 12.4.3.4.6.5.2 EPWM-Chopper Duty Cycle Control
             7. 12.4.3.4.7  EPWM Trip-Zone (TZ) Submodule
                1. 12.4.3.4.7.1 Overview
                2. 12.4.3.4.7.2 Controlling and Monitoring the EPWM Trip-Zone Submodule
                3. 12.4.3.4.7.3 Operational Highlights for the EPWM Trip-Zone Submodule
                4. 12.4.3.4.7.4 Generating EPWM Trip-Event Interrupts
             8. 12.4.3.4.8  EPWM Event-Trigger (ET) Submodule
                1. 12.4.3.4.8.1 Overview
                2. 12.4.3.4.8.2 Controlling and Monitoring the EPWM Event-Trigger Submodule
                3. 12.4.3.4.8.3 Operational Overview of the EPWM Event-Trigger Submodule
                4. 12.4.3.4.8.4 Operation Overview of the EPWM SOCx Pulse Generator
             9. 12.4.3.4.9  EPWM Functional Register Groups
             10. 12.4.3.4.10 Proper EPWM Interrupt Initialization Procedure
       4. 12.4.4 Enhanced Quadrature Encoder Pulse (EQEP) Module
          1. 12.4.4.1 EQEP Overview
             1. 12.4.4.1.1 EQEP Features
             2. 12.4.4.1.2 Unsupported Features
             3.        2622
          2. 12.4.4.2 EQEP Environment
             1. 12.4.4.2.1 EQEP I/O Interface
          3. 12.4.4.3 Integration
          4. 12.4.4.4 EQEP Functional Description
             1. 12.4.4.4.1 EQEP Inputs
             2. 12.4.4.4.2 EQEP Quadrature Decoder Unit (QDU)
                1. 12.4.4.4.2.1 EQEP Position Counter Input Modes
                   1. 12.4.4.4.2.1.1 Quadrature Count Mode
                   2. 12.4.4.4.2.1.2 EQEP Direction-count Mode
                   3. 12.4.4.4.2.1.3 EQEP Up-Count Mode
                   4. 12.4.4.4.2.1.4 EQEP Down-Count Mode
                2. 12.4.4.4.2.2 EQEP Input Polarity Selection
                3. 12.4.4.4.2.3 EQEP Position-Compare Sync Output
             3. 12.4.4.4.3 EQEP Position Counter and Control Unit (PCCU)
                1. 12.4.4.4.3.1 EQEP Position Counter Operating Modes
                   1. 12.4.4.4.3.1.1 EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
                   2. 12.4.4.4.3.1.2 EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b01)
                   3. 12.4.4.4.3.1.3 Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
                   4. 12.4.4.4.3.1.4 Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
                2. 12.4.4.4.3.2 EQEP Position Counter Latch
                   1. 12.4.4.4.3.2.1 Index Event Latch
                   2. 12.4.4.4.3.2.2 EQEP Strobe Event Latch
                3. 12.4.4.4.3.3 EQEP Position Counter Initialization
                4. 12.4.4.4.3.4 EQEP Position-Compare Unit
             4. 12.4.4.4.4 EQEP Edge Capture Unit
             5. 12.4.4.4.5 EQEP Watchdog
             6. 12.4.4.4.6 Unit Timer Base
             7. 12.4.4.4.7 EQEP Interrupt Structure
             8. 12.4.4.4.8 Summary of EQEP Functional Registers
    5. 12.5 Audio Peripherals
       1. 12.5.1 Audio Tracking Logic (ATL)
          1. 12.5.1.1 ATL Overview
             1. 12.5.1.1.1 ATL Features Overview
             2. 12.5.1.1.2 ATL Ports
       2. 12.5.2 Multichannel Audio Serial Port (MCASP)
          1. 12.5.2.1 MCASP Overview
             1. 12.5.2.1.1 MCASP Features
             2.        2660
             3. 12.5.2.1.2 Unsupported Features
          2. 12.5.2.2 MCASP Environment
             1. 12.5.2.2.1 MCASP Signals
             2. 12.5.2.2.2 MCASP Protocols and Data Formats
                1. 12.5.2.2.2.1 Protocols Supported
                2. 12.5.2.2.2.2 Definition of Terms
                3. 12.5.2.2.2.3 TDM Format
                4. 12.5.2.2.2.4 I2S Format
                5. 12.5.2.2.2.5 S/PDIF Coding Format
                   1. 12.5.2.2.2.5.1 Biphase-Mark Code
                   2. 12.5.2.2.2.5.2 S/PDIF Subframe Format
                   3. 12.5.2.2.2.5.3 Frame Format
          3. 12.5.2.3 Integration
          4. 12.5.2.4 MCASP Functional Description
             1. 12.5.2.4.1  MCASP Block Diagram
             2. 12.5.2.4.2  MCASP Clock and Frame-Sync Configurations
                1. 12.5.2.4.2.1 MCASP Transmit Clock
                2. 12.5.2.4.2.2 MCASP Receive Clock
                3. 12.5.2.4.2.3 Frame-Sync Generator
                4. 12.5.2.4.2.4 Synchronous and Asynchronous Transmit and Receive Operations
             3. 12.5.2.4.3  MCASP Serializers
             4. 12.5.2.4.4  MCASP Format Units
                1. 12.5.2.4.4.1 Transmit Format Unit
                   1. 12.5.2.4.4.1.1 TDM Mode Transmission Data Alignment Settings
                   2. 12.5.2.4.4.1.2 DIT Mode Transmission Data Alignment Settings
                2. 12.5.2.4.4.2 Receive Format Unit
                   1. 12.5.2.4.4.2.1 TDM Mode Reception Data Alignment Settings
             5. 12.5.2.4.5  MCASP State-Machines
             6. 12.5.2.4.6  MCASP TDM Sequencers
             7. 12.5.2.4.7  MCASP Software Reset
             8. 12.5.2.4.8  MCASP Power Management
             9. 12.5.2.4.9  MCASP Transfer Modes
                1. 12.5.2.4.9.1 Burst Transfer Mode
                2. 12.5.2.4.9.2 Time-Division Multiplexed (TDM) Transfer Mode
                   1. 12.5.2.4.9.2.1 TDM Time Slots Generation and Processing
                   2. 12.5.2.4.9.2.2 Special 384-Slot TDM Mode for Connection to External DIR
                3. 12.5.2.4.9.3 DIT Transfer Mode
                   1. 12.5.2.4.9.3.1 Transmit DIT Encoding
                   2. 12.5.2.4.9.3.2 Transmit DIT Clock and Frame-Sync Generation
                   3. 12.5.2.4.9.3.3 DIT Channel Status and User Data Register Files
             10. 12.5.2.4.10 MCASP Data Transmission and Reception
                 1. 12.5.2.4.10.1 Data Ready Status and Event/Interrupt Generation
                    1. 12.5.2.4.10.1.1 Transmit Data Ready
                    2. 12.5.2.4.10.1.2 Receive Data Ready
                    3. 12.5.2.4.10.1.3 Transfers Through the Data Port (DATA)
                    4. 12.5.2.4.10.1.4 Transfers Through the Configuration Bus (CFG)
                    5. 12.5.2.4.10.1.5 Using a Device CPU for MCASP Servicing
                    6. 12.5.2.4.10.1.6 Using the DMA for MCASP Servicing
             11. 12.5.2.4.11 MCASP Audio FIFO (AFIFO)
                 1. 12.5.2.4.11.1 AFIFO Data Transmission
                    1. 12.5.2.4.11.1.1 Transmit DMA Event Pacer
                 2. 12.5.2.4.11.2 AFIFO Data Reception
                    1. 12.5.2.4.11.2.1 Receive DMA Event Pacer
                 3. 12.5.2.4.11.3 Arbitration Between Transmit and Receive DMA Requests
             12. 12.5.2.4.12 MCASP Events and Interrupt Requests
                 1. 12.5.2.4.12.1 Transmit Data Ready Event and Interrupt
                 2. 12.5.2.4.12.2 Receive Data Ready Event and Interrupt
                 3. 12.5.2.4.12.3 Error Interrupt
                 4. 12.5.2.4.12.4 Multiple Interrupts
             13. 12.5.2.4.13 MCASP DMA Requests
             14. 12.5.2.4.14 MCASP Loopback Modes
                 1. 12.5.2.4.14.1 Loopback Mode Configurations
             15. 12.5.2.4.15 MCASP Error Reporting
                 1. 12.5.2.4.15.1 Buffer Underrun Error -Transmitter
                 2. 12.5.2.4.15.2 Buffer Overrun Error-Receiver
                 3. 12.5.2.4.15.3 DATA Port Error - Transmitter
                 4. 12.5.2.4.15.4 DATA Port Error - Receiver
                 5. 12.5.2.4.15.5 Unexpected Frame Sync Error
                 6. 12.5.2.4.15.6 Clock Failure Detection
                    1. 12.5.2.4.15.6.1 Clock Failure Check Startup
                    2. 12.5.2.4.15.6.2 Transmit Clock Failure Check and Recovery
                    3. 12.5.2.4.15.6.3 Receive Clock Failure Check and Recovery
          5. 12.5.2.5 MCASP Programming Guide
             1. 12.5.2.5.1 MCASP Global Initialization
                1. 12.5.2.5.1.1 Surrounding Modules Global Initialization
                2. 12.5.2.5.1.2 MCASP Global Initialization
                   1. 12.5.2.5.1.2.1 Main Sequence – MCASP Global Initialization for DIT-Transmission
                      1. 12.5.2.5.1.2.1.1 Subsequence – Transmit Format Unit Configuration for DIT-Transmission
                      2. 12.5.2.5.1.2.1.2 Subsequence – Transmit Frame Synchronization Generator Configuration for DIT-Transmission
                      3. 12.5.2.5.1.2.1.3 Subsequence – Transmit Clock Generator Configuration for DIT-Transmission
                      4. 12.5.2.5.1.2.1.4 Subsequence - MCASP Pins Functional Configuration
                      5. 12.5.2.5.1.2.1.5 Subsequence – DIT-specific Subframe Fields Configuration
                   2. 12.5.2.5.1.2.2 Main Sequence – MCASP Global Initialization for TDM-Reception
                      1. 12.5.2.5.1.2.2.1 Subsequence – Receive Format Unit Configuration in TDM Mode
                      2. 12.5.2.5.1.2.2.2 Subsequence – Receive Frame Synchronization Generator Configuration in TDM Mode
                      3. 12.5.2.5.1.2.2.3 Subsequence – Receive Clock Generator Configuration
                      4. 12.5.2.5.1.2.2.4 Subsequence—MCASP Receiver Pins Functional Configuration
                   3. 12.5.2.5.1.2.3 Main Sequence – MCASP Global Initialization for TDM -Transmission
                      1. 12.5.2.5.1.2.3.1 Subsequence – Transmit Format Unit Configuration in TDM Mode
                      2. 12.5.2.5.1.2.3.2 Subsequence – Transmit Frame Synchronization Generator Configuration in TDM Mode
                      3. 12.5.2.5.1.2.3.3 Subsequence – Transmit Clock Generator Configuration for TDM Cases
                      4. 12.5.2.5.1.2.3.4 Subsequence—MCASP Transmit Pins Functional Configuration
             2. 12.5.2.5.2 MCASP Operational Modes Configuration
                1. 12.5.2.5.2.1 MCASP Transmission Modes
                   1. 12.5.2.5.2.1.1 Main Sequence – MCASP DIT- /TDM- Polling Transmission Method
                   2. 12.5.2.5.2.1.2 Main Sequence – MCASP DIT- /TDM - Interrupt Transmission Method
                   3. 12.5.2.5.2.1.3 Main Sequence –MCASP DIT- /TDM - Mode DMA Transmission Method
                2. 12.5.2.5.2.2 MCASP Reception Modes
                   1. 12.5.2.5.2.2.1 Main Sequence – MCASP Polling Reception Method
                   2. 12.5.2.5.2.2.2 Main Sequence – MCASP TDM - Interrupt Reception Method
                   3. 12.5.2.5.2.2.3 Main Sequence – MCASP TDM - Mode DMA Reception Method
                3. 12.5.2.5.2.3 MCASP Event Servicing
                   1. 12.5.2.5.2.3.1 MCASP DIT-/TDM- Transmit Interrupt Events Servicing
                   2. 12.5.2.5.2.3.2 MCASP TDM- Receive Interrupt Events Servicing
                   3. 12.5.2.5.2.3.3 Subsequence – MCASP DIT-/TDM -Modes Transmit Error Handling
                   4. 12.5.2.5.2.3.4 Subsequence – MCASP Receive Error Handling
    6. 12.6 Camera Peripherals
       1. 12.6.1 Camera Serial Interface Receiver (CSI_RX_IF)
          1. 12.6.1.1 CSI_RX_IF Overview
             1. 12.6.1.1.1 CSI_RX_IF Features
             2. 12.6.1.1.2 Unsupported Features
             3.        2772
          2. 12.6.1.2 CSI_RX_IF Environment
          3. 12.6.1.3 Integration
          4. 12.6.1.4 CSI_RX_IF Functional Description
             1. 12.6.1.4.1 CSI_RX_IF Block Diagram
             2. 12.6.1.4.2 CSI_RX_IF Hardware and Software Reset
             3. 12.6.1.4.3 CSI_RX_IF Clock Configuration
             4. 12.6.1.4.4 CSI_RX_IF Interrupt Events
             5. 12.6.1.4.5 CSI_RX_IF Data Memory Organization Details
             6. 12.6.1.4.6 CSI_RX_IF PSI_L (DMA) Interface
                1. 12.6.1.4.6.1 PSI_L DMA framing
                2. 12.6.1.4.6.2 PSI_L DMA error handling due to FIFO overflow
             7. 12.6.1.4.7 CSI_RX_IF ECC Protection Support
             8. 12.6.1.4.8 CSI_RX_IF Programming Guide
                1. 12.6.1.4.8.1  Overview
                2. 12.6.1.4.8.2  Controller Configuration
                3. 12.6.1.4.8.3  Power on Configuration
                4. 12.6.1.4.8.4  Stream Start and Stop
                5. 12.6.1.4.8.5  Error Control With Soft Resets
                6. 12.6.1.4.8.6  Stream Error Detected – No Error Bypass Mode
                7. 12.6.1.4.8.7  Stream Error Detected – Error Bypass Mode
                8. 12.6.1.4.8.8  Stream Error Detected – Soft Reset Recovery
                9. 12.6.1.4.8.9  Stream Monitor Configuration
                10. 12.6.1.4.8.10 Stream Monitor Frame Capture Control
                11. 12.6.1.4.8.11 Stream Monitor Timer interrupt
                12. 12.6.1.4.8.12 Stream Monitor Line/Byte Counters Interrupt
                13. 12.6.1.4.8.13 Example Controller Programming Sequence (Single Stream Operation)
                14. 12.6.1.4.8.14 CSI_RX_IF Programming Restrictions
                15. 12.6.1.4.8.15 CSI_RX_IF Real-time operating requirements
       2. 12.6.2 MIPI D-PHY Receiver (DPHY_RX)
          1. 12.6.2.1 DPHY_RX Overview
             1. 12.6.2.1.1 DPHY_RX Features
             2. 12.6.2.1.2 Unsupported Features
             3.        2805
          2. 12.6.2.2 DPHY_RX Environment
          3. 12.6.2.3 Integration
          4. 12.6.2.4 DPHY_RX Functional Description
             1. 12.6.2.4.1 DPHY_RX Programming Guide
                1. 12.6.2.4.1.1 Overview
                2. 12.6.2.4.1.2 Initial Configuration Programming
                   1. 12.6.2.4.1.2.1 Start-up Sequence Timing Diagram
                3. 12.6.2.4.1.3 Common Configuration
                4. 12.6.2.4.1.4 Lane Configuration
       3. 12.6.3 MIPI D-PHY Transmitter (DPHY_TX)
          1. 12.6.3.1 DPHY_TX Subsystem Overview
             1. 12.6.3.1.1 DPHY_TX Features
             2. 12.6.3.1.2 Unsupported Features
             3.        2819
          2. 12.6.3.2 Integration
       4. 12.6.4 Camera Streaming Interface Transmitter (CSI_TX_IF)
          1. 12.6.4.1 CSI_TX_IF Overview
             1. 12.6.4.1.1 CSI_TX_IF Ports
          2. 12.6.4.2 CSI_TX_IF Features
             1. 12.6.4.2.1 CSI_TX_IF Legacy Compatibility
          3. 12.6.4.3 CSI_TX_IF Environment
          4. 12.6.4.4 CSI_TX_IF Functional Description
             1. 12.6.4.4.1 CSI_TX_IF Block Diagram
             2. 12.6.4.4.2 CSI_TX_IF Hardware and Software Reset
             3. 12.6.4.4.3 CSI_TX_IF Clock Configuration
             4. 12.6.4.4.4 CSI_TX_IF Interrupt Events
             5. 12.6.4.4.5 CSI_TX_IF Data Memory Organization Details
             6. 12.6.4.4.6 CSI_TX_IF PSI_L (DMA) Interface
             7. 12.6.4.4.7 CSI_TX_IF ECC Protection Support
          5. 12.6.4.5 CSI_TX_IF Programming Guide
             1. 12.6.4.5.1  CSI_TX_IF Programming (Configuration Mode)
             2. 12.6.4.5.2  CSI_TX_IF System Initialization Programming
             3. 12.6.4.5.3  CSI_TX_IF Lane Control Programming
             4. 12.6.4.5.4  CSI_TX_IF Virtual Channel and Data Type Management
                1. 12.6.4.5.4.1 CSI_TX_IF Data Type Interleaving
                2. 12.6.4.5.4.2 CSI_TX_IF Data Type Interleaving with Multiple Interfaces
                3. 12.6.4.5.4.3 CSI_TX_IF Virtual Channel Interleaving
                4. 12.6.4.5.4.4 CSI_TX_IF Virtual Channel and Data Type Interleaving
             5. 12.6.4.5.5  CSI_TX_IF Line Control
                1. 12.6.4.5.5.1 CSI_TX_IF Line Control Arbitration
             6. 12.6.4.5.6  CSI_TX_IF Lane Manager FSM
             7. 12.6.4.5.7  CSI_TX_IF Data Lane Control FSM
             8. 12.6.4.5.8  CSI_TX_IF Application Examples
                1. 12.6.4.5.8.1 CSI_TX_IF D-PHY Control and Configuration
                2. 12.6.4.5.8.2 CSI_TX_IF Clock and Data Lane Enable
                3. 12.6.4.5.8.3 CSI_TX_IF DP/DN Signal Swap
             9. 12.6.4.5.9  CSI_TX_IF DPHY_TX Status
             10. 12.6.4.5.10 CSI_TX_IF ULPS Operation
             11. 12.6.4.5.11 CSI_TX_IF System Frame Rate Measurement
             12. 12.6.4.5.12 CSI_TX_IF Configuration for PSI_L
             13. 12.6.4.5.13 CSI_TX_IF Configuration for Color Bar
             14. 12.6.4.5.14 CSI_TX_IF Error Recovery
             15. 12.6.4.5.15 CSI_TX_IF Power up/down Sequence
    7. 12.7 Timer Modules
       1. 12.7.1 Global Timebase Counter (GTC)
          1. 12.7.1.1 Global Timebase Counter (GTC)
             1. 12.7.1.1.1 GTC Overview
                1. 12.7.1.1.1.1 GTC Features
                2. 12.7.1.1.1.2 Unsupported Features
                3.         2865
          2. 12.7.1.2 GTC Functional Description
             1. 12.7.1.2.1 GTC Block Diagram
             2. 12.7.1.2.2 GTC Counter
                1. 12.7.1.2.2.1 Steps to Clear the Counter Value to Zero
             3. 12.7.1.2.3 GTC Register Partitioning
       2. 12.7.2 RTI-Windowed Watchdog Timer (WWDT)
          1. 12.7.2.1 RTI Features
          2. 12.7.2.2 Unsupported Features
          3.       2874
          4. 12.7.2.3 RTI Functional Description
             1. 12.7.2.3.1 RTI Digital Windowed Watchdog
                1. 12.7.2.3.1.1 RTI Debug Mode Behavior
                2. 12.7.2.3.1.2 RTI Low Power Mode Operation
             2. 12.7.2.3.2 RTI Digital Watchdog
             3. 12.7.2.3.3 RTI Counter Operation
       3. 12.7.3 Real-Time Clock (RTC)
          1. 12.7.3.1 RTC Overview
             1. 12.7.3.1.1 RTC Features
             2. 12.7.3.1.2 Unsupported Features
             3.        2885
          2. 12.7.3.2 RTC Integration
          3. 12.7.3.3 RTC Functional Description
             1. 12.7.3.3.1 RTC Block Diagram
                1. 12.7.3.3.1.1 DIG_CORE uARCH
                2. 12.7.3.3.1.2 DIG_ON uARCH
                3. 12.7.3.3.1.3 ISO_LVL uARCH
                4. 12.7.3.3.1.4 DIG_CORE to DIG_ON updates uARCH
             2. 12.7.3.3.2 CPU Interrupt Support
                1. 12.7.3.3.2.1 CPU Interrupts
             3. 12.7.3.3.3 Programming Usage Guide
                1. 12.7.3.3.3.1 No Analog Support
                2. 12.7.3.3.3.2 With Analog Support
                   1. 12.7.3.3.3.2.1 MMR Spurious WRT Protection
                   2. 12.7.3.3.3.2.2 Crystal Compensation
             4. 12.7.3.3.4 Scratch Registers
             5. 12.7.3.3.5 KS3 Clock Stop Protocol
       4. 12.7.4 Timers
          1. 12.7.4.1 Timers Overview
             1. 12.7.4.1.1 Timers Features
             2. 12.7.4.1.2 Unsupported Features
             3.        2906
          2. 12.7.4.2 Timers Environment
             1. 12.7.4.2.1 Timer External System Interface
          3. 12.7.4.3 Integration
          4. 12.7.4.4 Timers Functional Description
             1. 12.7.4.4.1  Timer Block Diagram
             2. 12.7.4.4.2  Timer Power Management
                1. 12.7.4.4.2.1 Wake-Up Capability
             3. 12.7.4.4.3  Timer Software Reset
             4. 12.7.4.4.4  Timer Interrupts
             5. 12.7.4.4.5  Timer Mode Functionality
                1. 12.7.4.4.5.1 1-ms Tick Generation
             6. 12.7.4.4.6  Timer Capture Mode Functionality
             7. 12.7.4.4.7  Timer Compare Mode Functionality
             8. 12.7.4.4.8  Timer Prescaler Functionality
             9. 12.7.4.4.9  Timer Pulse-Width Modulation
             10. 12.7.4.4.10 Timer Counting Rate
             11. 12.7.4.4.11 Timer Under Emulation
             12. 12.7.4.4.12 Accessing Timer Registers
                 1. 12.7.4.4.12.1 Writing to Timer Registers
                    1. 12.7.4.4.12.1.1 Write Posting Synchronization Mode
                    2. 12.7.4.4.12.1.2 Write Nonposting Synchronization Mode
                 2. 12.7.4.4.12.2 Reading From Timer Counter Registers
                    1. 12.7.4.4.12.2.1 Read Posted
                    2. 12.7.4.4.12.2.2 Read Non-Posted
             13. 12.7.4.4.13 Timer Posted Mode Selection
          5. 12.7.4.5 Timers Low-Level Programming Models
             1. 12.7.4.5.1 Timer Global Initialization
                1. 12.7.4.5.1.1 Main Sequence – Timer Module Global Initialization
             2. 12.7.4.5.2 Timer Operational Mode Configuration
                1. 12.7.4.5.2.1 Timer Mode
                   1. 12.7.4.5.2.1.1 Main Sequence – Timer Mode Configuration
                2. 12.7.4.5.2.2 Timer Compare Mode
                   1. 12.7.4.5.2.2.1 Main Sequence – Timer Compare Mode Configuration
                3. 12.7.4.5.2.3 Timer Capture Mode
                   1. 12.7.4.5.2.3.1 Main Sequence – Timer Capture Mode Configuration
                   2. 12.7.4.5.2.3.2 Subsequence – Initialize Capture Mode
                   3. 12.7.4.5.2.3.3 Subsequence – Detect Event
                4. 12.7.4.5.2.4 Timer PWM Mode
                   1. 12.7.4.5.2.4.1 Main Sequence – Timer PWM Mode Configuration
    8. 12.8 Internal Diagnostics Modules
       1. 12.8.1 Dual Clock Comparator (DCC)
          1. 12.8.1.1 DCC Overview
             1. 12.8.1.1.1 DCC Features
             2. 12.8.1.1.2 Unsupported Features
             3.        2951
          2. 12.8.1.2 DCC Functional Description
             1. 12.8.1.2.1 DCC Counter Operation
             2. 12.8.1.2.2 DCC Low Power Mode Operation
             3. 12.8.1.2.3 DCC Suspend Mode Behavior
             4. 12.8.1.2.4 DCC Single-Shot Mode
             5. 12.8.1.2.5 DCC Continuous mode
                1. 12.8.1.2.5.1 DCC Continue on Error
                2. 12.8.1.2.5.2 DCC Error Count
             6. 12.8.1.2.6 DCC Control and count hand-off across clock domains
             7. 12.8.1.2.7 DCC Error Trajectory record
                1. 12.8.1.2.7.1 DCC FIFO capturing for Errors
                2. 12.8.1.2.7.2 DCC FIFO in continuous capture mode
                3. 12.8.1.2.7.3 DCC FIFO Details
                4. 12.8.1.2.7.4 DCC FIFO Debug mode behavior
             8. 12.8.1.2.8 DCC Count read registers
       2. 12.8.2 Error Signaling Module (ESM)
          1. 12.8.2.1 ESM Overview
             1. 12.8.2.1.1 ESM Features
             2. 12.8.2.1.2 Unsupported Features
             3.        2971
          2. 12.8.2.2 ESM Environment
          3. 12.8.2.3 Integration
          4. 12.8.2.4 ESM Functional Description
             1. 12.8.2.4.1 ESM Interrupt Requests
                1. 12.8.2.4.1.1 ESM Configuration Error Interrupt
                2. 12.8.2.4.1.2 ESM Low Priority Error Interrupt
                   1. 12.8.2.4.1.2.1 ESM Low Priority Error Level Event
                   2. 12.8.2.4.1.2.2 ESM Low Priority Error Pulse Event
                3. 12.8.2.4.1.3 ESM High Priority Error Interrupt
                   1. 12.8.2.4.1.3.1 ESM High Priority Error Level Event
                   2. 12.8.2.4.1.3.2 ESM High Priority Error Pulse Event
             2. 12.8.2.4.2 ESM Error Event Inputs
             3. 12.8.2.4.3 ESM Error Pin Output
             4. 12.8.2.4.4 PWM Mode
             5. 12.8.2.4.5 ESM Minimum Time Interval
             6. 12.8.2.4.6 ESM Protection for Registers
             7. 12.8.2.4.7 ESM Clock Stop
       3. 12.8.3 Memory Cyclic Redundancy Check (MCRC) Controller
          1. 12.8.3.1 MCRC Overview
             1. 12.8.3.1.1 MCRC Features
             2. 12.8.3.1.2 Unsupported Features
             3.        2993
          2. 12.8.3.2 MCRC Functional Description
             1. 12.8.3.2.1  MCRC Block Diagram
             2. 12.8.3.2.2  MCRC General Operation
             3. 12.8.3.2.3  MCRC Modes of Operation
                1. 12.8.3.2.3.1 AUTO Mode
                2. 12.8.3.2.3.2 Semi-CPU Mode
                3. 12.8.3.2.3.3 Full-CPU Mode
             4. 12.8.3.2.4  PSA Signature Register
             5. 12.8.3.2.5  PSA Sector Signature Register
             6. 12.8.3.2.6  CRC Value Register
             7. 12.8.3.2.7  Raw Data Register
             8. 12.8.3.2.8  Example DMA Controller Setup
                1. 12.8.3.2.8.1 AUTO Mode Using Hardware Timer Trigger
                2. 12.8.3.2.8.2 AUTO Mode Using Software Trigger
                3. 12.8.3.2.8.3 Semi-CPU Mode Using Hardware Timer Trigger
             9. 12.8.3.2.9  Pattern Count Register
             10. 12.8.3.2.10 Sector Count Register/Current Sector Register
             11. 12.8.3.2.11 Interrupts
                 1. 12.8.3.2.11.1 Overrun Interrupt
                 2. 12.8.3.2.11.2 Timeout Interrupt
                 3. 12.8.3.2.11.3 Underrun Interrupt
                 4. 12.8.3.2.11.4 Compression Complete Interrupt
                 5. 12.8.3.2.11.5 Interrupt Offset Register
                 6. 12.8.3.2.11.6 Error Handling
             12. 12.8.3.2.12 Power Down Mode
             13. 12.8.3.2.13 Emulation
          3. 12.8.3.3 MCRC Programming Examples
             1. 12.8.3.3.1 Example: Auto Mode Using Time Based Event Triggering
                1. 12.8.3.3.1.1 DMA Setup
                2. 12.8.3.3.1.2 Timer Setup
                3. 12.8.3.3.1.3 CRC Setup
             2. 12.8.3.3.2 Example: Auto Mode Without Using Time Based Triggering
                1. 12.8.3.3.2.1 DMA Setup
                2. 12.8.3.3.2.2 CRC Setup
             3. 12.8.3.3.3 Example: Semi-CPU Mode
                1. 12.8.3.3.3.1 DMA Setup
                2. 12.8.3.3.3.2 Timer Setup
                3. 12.8.3.3.3.3 CRC Setup
             4. 12.8.3.3.4 Example: Full-CPU Mode
                1. 12.8.3.3.4.1 CRC Setup
       4. 12.8.4 ECC Aggregator
          1. 12.8.4.1 ECC Aggregator Overview
             1. 12.8.4.1.1 ECC Aggregator Features
             2. 12.8.4.1.2 Unsupported Features
             3.        3038
          2. 12.8.4.2 Integration
          3. 12.8.4.3 ECC Aggregator Functional Description
             1. 12.8.4.3.1 ECC Aggregator Block Diagram
             2. 12.8.4.3.2 ECC Aggregator Register Groups
             3. 12.8.4.3.3 Read Access to the ECC Control and Status Registers
             4. 12.8.4.3.4 Serial Write Operation
             5. 12.8.4.3.5 Interrupts
             6. 12.8.4.3.6 Inject Only Mode
          4. 12.8.4.4 ECC Aggregator Configurations
             1.        3048
             2.        3049
             3.        3050
             4.        3051
             5.        3052
             6.        3053
             7.        3054
             8.        3055
             9.        3056
             10.        3057
             11.        3058
             12.        3059
             13.        3060
             14.        3061
             15.        3062
             16.        3063
             17.        3064
             18.        3065
             19.        3066
             20.        3067
             21.        3068
             22.        3069
             23.        3070
             24.        3071
             25.        3072
             26.        3073
             27.        3074
             28.        3075
             29.        3076
             30.        3077
             31.        3078
       5. 12.8.5 Interconnect ECC Aggregators
          1.       3080
          2.       3081
          3.       3082
          4.       3083
          5.       3084
          6.       3085
    9. 12.9 Display Subsystem and Peripherals
       1. 12.9.1 Display Subsystem (DSS)
          1. 12.9.1.1 DSS Overview
             1. 12.9.1.1.1 DSS Features
             2.        3090
             3. 12.9.1.1.2 Unsupported Features
          2. 12.9.1.2 DSS Environment
             1. 12.9.1.2.1 DSS Parallel Interface
                1. 12.9.1.2.1.1 Pixel Data Formats
                2. 12.9.1.2.1.2 Display Timing Diagrams
             2. 12.9.1.2.2 DSS LVDS Interface
          3. 12.9.1.3 Integration
          4. 12.9.1.4 DSS Functional Description
             1. 12.9.1.4.1 DISPC Functional Description
                1. 12.9.1.4.1.1  DISPC Overview
                2. 12.9.1.4.1.2  DISPC Clocks
                3. 12.9.1.4.1.3  DISPC Resets
                4. 12.9.1.4.1.4  DISPC Power Management
                5. 12.9.1.4.1.5  DISPC Interrupt Requests
                6. 12.9.1.4.1.6  DISPC DMA Engine
                   1. 12.9.1.4.1.6.1 DISPC DMA Addressing and Bursts
                   2. 12.9.1.4.1.6.2 DISPC Read DMA Buffers
                   3. 12.9.1.4.1.6.3 DISPC Flip/Mirror Support
                   4. 12.9.1.4.1.6.4 DISPC DMA Predecimation
                   5. 12.9.1.4.1.6.5 DISPC DMA MFLAG Mechanism
                   6. 12.9.1.4.1.6.6 DISPC DMA Priority Requests Control
                   7. 12.9.1.4.1.6.7 DISPC DMA Arbitration
                   8. 12.9.1.4.1.6.8 DISPC DMA Power Modes
                      1. 12.9.1.4.1.6.8.1 DISPC DMA Low Power Mode
                      2. 12.9.1.4.1.6.8.2 DISPC DMA Ultra-Low Power Mode
                7. 12.9.1.4.1.7  DISPC Pixel Data Formats
                8. 12.9.1.4.1.8  DISPC Video Pipelines
                   1. 12.9.1.4.1.8.1 DISPC VID Replication Logic
                   2. 12.9.1.4.1.8.2 DISPC VID VC-1 Range Mapping Unit
                   3. 12.9.1.4.1.8.3 DISPC VID Color Look-Up Table (CLUT)
                   4. 12.9.1.4.1.8.4 DISPC VID Chrominance Resampling
                      1. 12.9.1.4.1.8.4.1 Chrominance Resampling for VID Pipeline
                      2. 12.9.1.4.1.8.4.2 Chrominance Resampling for VIDL1 Pipeline
                   5. 12.9.1.4.1.8.5 DISPC VID Scaler Unit
                   6. 12.9.1.4.1.8.6 DISPC VID Color Space Conversion YUV to RGB
                   7. 12.9.1.4.1.8.7 DISPC VID Brightness/Contrast/Saturation/Hue Control
                   8. 12.9.1.4.1.8.8 DISPC VID Luma Key Support
                9. 12.9.1.4.1.9  DISPC Overlay Managers
                   1. 12.9.1.4.1.9.1 DISPC Overlay Input Selector
                   2. 12.9.1.4.1.9.2 DISPC Overlay Mechanism
                      1. 12.9.1.4.1.9.2.1 Overlay Alpha Blender
                      2. 12.9.1.4.1.9.2.2 Overlay Transparency Color Keys
                   3. 12.9.1.4.1.9.3 Overlay 3D Support
                   4. 12.9.1.4.1.9.4 Overlay Color Bar Insertion
                10. 12.9.1.4.1.10 DISPC Video Port Outputs
                    1. 12.9.1.4.1.10.1 DISPC VP Gamma Correction Unit
                    2. 12.9.1.4.1.10.2 DISPC VP Color Phase Rotation Unit
                    3. 12.9.1.4.1.10.3 DISPC VP Color Space Conversion - RGB to YUV
                    4. 12.9.1.4.1.10.4 DISPC VP BT.656 and BT.1120 Modes
                       1. 12.9.1.4.1.10.4.1 DISPC BT Mode Blanking
                       2. 12.9.1.4.1.10.4.2 DISPC BT Mode EAV and SAV
                    5. 12.9.1.4.1.10.5 DISPC VP Spatial/Temporal Dithering
                    6. 12.9.1.4.1.10.6 DISPC VP Multiple Cycle Output Format (TDM)
                    7. 12.9.1.4.1.10.7 DISPC VP Timing Generator and Display Panel Settings
                11. 12.9.1.4.1.11 DISPC Safety Features
                    1. 12.9.1.4.1.11.1 Safety Check Regions
                    2. 12.9.1.4.1.11.2 Safety Signature Generator Using MISR
                    3. 12.9.1.4.1.11.3 Safety Checks
                    4. 12.9.1.4.1.11.4 Safety Check Limitations
                12. 12.9.1.4.1.12 DISPC Security Management
                    1. 12.9.1.4.1.12.1 Security Implementation
                    2. 12.9.1.4.1.12.2 Secure Mode Configuration
                13. 12.9.1.4.1.13 DISPC Shadow Registers
             2. 12.9.1.4.2 OLDITX Functional Description
                1. 12.9.1.4.2.1 OLDITX Overview
                2. 12.9.1.4.2.2 OLDITX Clocks
                3. 12.9.1.4.2.3 OLDITX Resets
                4. 12.9.1.4.2.4 OLDITX Input Interface
                   1. 12.9.1.4.2.4.1 OLDITX 24-bit RGB Input
                   2. 12.9.1.4.2.4.2 OLDITX 18-bit RGB Input
                5. 12.9.1.4.2.5 OLDITX Output Mode Configuration
                6. 12.9.1.4.2.6 OLDITX Loopback Test Mode
       2. 12.9.2 MIPI Display Serial Interface (DSI) Controller
          1. 12.9.2.1 DSI Block Diagram
          2. 12.9.2.2 DSI Clocking
          3. 12.9.2.3 DSI Reset
          4. 12.9.2.4 DSI Power Management
          5. 12.9.2.5 DSI Interrupts
          6. 12.9.2.6 DSI Internal Interfaces
             1. 12.9.2.6.1 Video Input Interfaces
                1. 12.9.2.6.1.1 Pixel Mapping
             2. 12.9.2.6.2 DPI (Pixel Stream Interface)
                1. 12.9.2.6.2.1 Signals
             3. 12.9.2.6.3 SDI (Serial Data Interface)
                1. 12.9.2.6.3.1 Secure Display Support
          7. 12.9.2.7 DSI Programming Guide
             1. 12.9.2.7.1  Application Guidelines
                1. 12.9.2.7.1.1 Overview of a Display Subsystem
                2. 12.9.2.7.1.2 D-PHY And DSI Configuration
                3. 12.9.2.7.1.3 DSI Controller Initialization
                4. 12.9.2.7.1.4 Panel Configuration Using Command Mode
                5. 12.9.2.7.1.5 VIDEO Interface Configuration
             2. 12.9.2.7.2  Application Considerations
                1. 12.9.2.7.2.1 D-PHY Timings Control
                2. 12.9.2.7.2.2 Control Block
                3. 12.9.2.7.2.3 Video Coherency
             3. 12.9.2.7.3  Start-up Procedure
             4. 12.9.2.7.4  Interrupt Management
                1. 12.9.2.7.4.1 Error and Status Registers
                2. 12.9.2.7.4.2 Interrupt Management for Direct Command Registers
             5. 12.9.2.7.5  Direct Command Usage
                1. 12.9.2.7.5.1 Trigger Mapping Information
                2. 12.9.2.7.5.2 Command Mode Settings
                3. 12.9.2.7.5.3 Bus Turnaround Sequence
                4. 12.9.2.7.5.4 Tearing Effect Control
                5. 12.9.2.7.5.5 Tearing Effect Control on Panels with Frame Buffer
                6. 12.9.2.7.5.6 Return Path Operation
                7. 12.9.2.7.5.7 EoT Packet Management
                8. 12.9.2.7.5.8 ECC Correction
                9. 12.9.2.7.5.9 LP Transmission and BTA
             6. 12.9.2.7.6  Low-power Management
             7. 12.9.2.7.7  Video Mode Settings
                1. 12.9.2.7.7.1 Video Stream Presentation
                2. 12.9.2.7.7.2 Video Stream Settings (VSG)
                3. 12.9.2.7.7.3 VCA Configuration
                4. 12.9.2.7.7.4 TVG Configuration
             8. 12.9.2.7.8  DPI To DSI Programming
                1. 12.9.2.7.8.1 DSI and DPHY Operation
                2. 12.9.2.7.8.2 Pixel Clock to TX_BYTE_CLK Variation
                3. 12.9.2.7.8.3 LP Operation
                4. 12.9.2.7.8.4 DPI Interface Burst Operation
             9. 12.9.2.7.9  Programming the DSITX Controller to Match the Incoming DPI Stream
                1. 12.9.2.7.9.1 Vertical Timing
                2. 12.9.2.7.9.2 Horizontal Timing for Non-Burst Mode with Sync Pulses
                3. 12.9.2.7.9.3 Event Mode Horizontal Timing
                4. 12.9.2.7.9.4 Burst Event Mode Horizontal Timing
                5. 12.9.2.7.9.5 Burst Mode Operation
                6. 12.9.2.7.9.6 Example Configurations
                7. 12.9.2.7.9.7 Stereoscopic Video Support
             10. 12.9.2.7.10 DSITX Video Stream Variable Refresh
15. 13On-Chip Debug
    1. 13.1 On-Chip Debug Overview
    2. 13.2 On-Chip Debug Features
    3.     3224
    4. 13.3 On-Chip Debug Functional Description
       1. 13.3.1  On-Chip Debug Block Diagram
       2. 13.3.2  Device Interfaces
          1. 13.3.2.1 JTAG Interface
          2. 13.3.2.2 Trigger and Debug Boot Mode Interface
          3. 13.3.2.3 Trace Port Interface
       3. 13.3.3  Debug and Boundary Scan Access and Control
       4. 13.3.4  Debug Boot Modes and Boundary Scan Compliance
       5. 13.3.5  Power, Reset, Clock Management
       6. 13.3.6  Debug Cross Triggering
       7. 13.3.7  WKUP_R5F Debug
       8. 13.3.8  A53SS0 Debug
       9. 13.3.9  SoC Debug and Trace
          1. 13.3.9.1 Software messaging trace
          2. 13.3.9.2 Debug-Aware Peripherals
          3. 13.3.9.3 Traffic Monitoring With Bus Probes
          4. 13.3.9.4 Global timestamping for trace
       10. 13.3.10 Trace Traffic
           1. 13.3.10.1 Trace Sources
           2. 13.3.10.2 Trace Infrasctructure
           3. 13.3.10.3 Trace Sinks
       11. 13.3.11 Application Support
16. 14Revision History