SPRAD21E May 2023 â February 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1
When a 32-bit, Single-Rank/Dual-Rank LPDDR4 is used, follow Balanced âTâ Topology for Address, CKE and CK signals routing.
When a 16-bit, Single-Rank LPDDR4 is used, follow the point-to-point topology. Connect the unused Data strobe pins (DDR0_DQS2..3 and DQS2..3_n) as per the AM62Ax / AM62Px LPDDR4 Board Design and Layout Guidelines recommendation.
The data signal connection topology is point-to-point for LPDDR4, and is categorized into different byte lanes.
VTT termination does not apply for LPDDR4. Terminations required for address/control signals are handled internally (on-die).