SPRAD21E May 2023 – February 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1
It is recommended to implement the device reset using a three input AND gate logic. One of the AND gate input is connected to the processor general purpose input/output (GPIO) pin. The AND gate input has provision for pullup and 0 Ω to isolate the GPIO for testing or debug. The other AND gate input can be the Main Domain POR (cold reset) status output (PORz_OUT) and Main Domain warm reset status output (RESETSTATz) Signals.
If a dual input AND gate is used, PORz_OUT or RESETSTATz can be connected as one of the inputs along with the processor GPIO input as the second input based on the use case. When more than one EPHY is used, it is recommended to provide provision to reset the EPHYs individually.
A pullup or pulldown at the output of the ANDing logic is recommended based on the EPHY reset pin configuration. The board designer needs to make sure the EPHYs are held in reset for a specified minimum reset hold time after the respective clocks are valid.
In case an ANDing logic is not used and the processor Main Domain warm reset status output (RESETSTATz) is used to reset the attached device, ensure the IO voltage level of the attached device matches the RESETSTATz IO voltage level. A level translator is recommended to match the IO voltage level.