SPRAD21E May 2023 – February 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1
LVCMOS inputs have slew rate requirements specified. Connecting slow ramp signal directly to the LVCMOS inputs or capacitors at the LVCMOS inputs is not recommended. When slow ramp input is applied, CMOS input will have shoot-through current that flows from VDD through the partially turned on P-channel transistor and the partially turned on N-channel transistor to VSS when the input is at mid-supply. Accumulated exposure to slow ramps could result in performance or reliability concerns.
LVCMOS output buffers were not designed to drive large capacitive loads. For LVCMOS type IOs when configured as output and connected to capacitive load, follow the data sheet recommendations for the allowed capacitor value or add series resistor to limit the current or perform simulations.