SPRAD21E May 2023 – February 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1
When two memory (DDR4) devices (2 X 8-bit) are used, each device would be connected to each data byte. The address/control signals would be connected in Fly-by topology with VTT termination.
Refer AM64x evaluation module for Sitara processors for implementing VTT termination.
It is recommended to perform board level simulations to ensure proper signal integrity.