Clock Buffers - easy clock distribution in any system

Low additive jitter and skew with highly flexible input/output formats

Universal and programmable buffers

  • Excellent skew and additive jitter performance
  • Accept multiple input formats
  • Selectable output levels
  • Dividers and delays
  • Configuration with pin strap or serial interface
  • Level translation
  • Reuse one device for multiple projects

Fanout buffers

  • Cost optimized solution
  • Scalable families available for all important signal standards
    • LVCMOS
    • LVDS
    • LVPECL
    • HCSL (PCIe)
    • CML
    • (LV)TTL

Zero delay buffers

  • Integrated PLL with feedback loop for delay compensation
  • Compensate flight time of long traces
  • Recondition poor clock signals without additional delay

Videos for Clock Buffers

WEBENCH® Clock Architect

TI's WEBENCH Clock Architect online design tool makes the designer’s life easier by generating complete clock-tree solutions. Multiple solutions are generated, each optimized for performance, cost or board space.


WEBENCH® Designer

Texas Instruments clock buffers make it easy to distribute clocks in any system. TI’s clock buffers combine low additive jitter and skew with highly flexible input/output formats covering LVPECL, LVDS, HCSL, CML and CMOS levels. The TI WEBENCH® online clock tree design tool makes it easy to select clock buffers for specific system needs.