The sinc filter consists of two stages: a variable-decimation, fixed-order sinc5 filter, followed by a variable-decimation, variable-order sinc filter. The first-stage filter is sinc5. The sinc5 stage filters and down-samples the modulator data (fCLK / 8 = 921.6 kHz) to 38400 SPS, 19200 SPS, and 14400 SPS by decimating to 24, 48, and 64, respectively. These data rates bypass the second filter stage and as a result have a sinc5 frequency response profile. The second filter stage receives the data from the first stage at 14400 SPS. The second stage reduces the data rate to produce output data of 7200 SPS to 2.5 SPS. The second stage is a variable-order sinc filter that is programmable.
The combined decimation ratio of the first and second stages determine the output data rate as follows: data rate = 921.6 kHz / (A · B). The filter order of the second stage affects the 50-Hz and 60-Hz rejection together with conversion latency. The high-order sinc filter yields the widest 50-Hz and 60-Hz response null widths, but correspondingly increases the conversion latency. The sinc order is programmed by the FILTER[2:0] bits of register MODE1. Table 9-3 lists the decimation ratio corresponding to the first and second filter stages (A and B, respectively) for each data rate. The data rate is programmed by the DR[3:0] bits of register MODE2.
|DATA RATE (SPS)(1)||DR[3:0] BITS OF REGISTER MODE2||FIRST-STAGE DECIMATION RATIO A||SECOND-STAGE DECIMATION RATIO B|