Sequence the power supplies in any order, but never allow and analog or digital inputs to exceed the respective analog or digital power-supplies without limiting the input fault current. The ADC remains in reset until both analog and digital power supplies exceed the respective power-on reset (POR) thresholds. Figure 9-52 shows the power-on reset sequence. After the power supplies have crossed the reset levels (including the internal 2-V LDO), the ADC resets (POR) and is ready for communication 65536 clock periods later (nominally 9 ms).
Delay communication for 50 ms after the power supplies have stabilized within the specified range to make sure the ADC is operational. In addition to POR, make sure that the reference voltage has fully settled before starting the conversions. When using a 1-µF reference capacitor allow a minimum of 50 ms for the internal reference to settle. External references may require additional settling time.