When a new conversion is started, the ADC provides an internal delay of 52 µs before the actual start of the conversion. This timed delay is provided to allow for the integrated, analog, antialias filter to settle. In some cases, more delay is required to allow for external settling effects. Program additional time by using bits DELAY[3:0] of the MODE register. The programable range is 8.7 µs to 8.8 ms in binary steps. As an alternative to using the programmable time delay, the initiation of the start condition can also be delayed as needed after an ADC configuration change. For CHOP or IDAC rotation modes, additional time delay may be necessary to allow for external settling effects, and can only be provided by the DELAY bits; see Table 9-38 for the delay settings.