The CS input resets the serial interface when taken high. However, applications that tie the CS pin low do not have the ability to reset the serial interface by using this pin. If a false SCLK occurs (for example, caused by a noise pulse or clocking glitch), the serial interface may inadvertently advance one or more bit positions, resulting in loss of synchronization to the external microcontroller. If loss of synchronization occurs, the interface does not respond correctly until the interface is reset.
For applications that tie CS low, the ADC provides a feature that automatically resets the serial interface in the event of a glitch. As shown in Figure 9-41, after the first SCLK low-to-high transition is detected by the ADC (either caused by a glitch or a normal SCLK input), if the ADC does not detect seven additional SCLK transitions within 65536 fCLK cycles (approximately 8.9 ms), the serial interface resets. After reset, the interface is ready for the next transaction four fCLK cycles later.
If the seven SCLK transitions are detected within the 65536 fCLK cycles, the serial interface is not reset, and the SCLK detection cycle restarts at the next SCLK transition.
If the serial interface loses synchronization to an external controller, reset the serial interface by holding SCLK low for 65536 fCLK cycles.
The serial interface autoreset function is enabled by the setting TIMEOUT = 1 (bit 3 of the INTERFACE register). The default mode is off.
|td(SCRS)||SCLK↑ transition to interface reset : delay time||TIMEOUT bit =1||65536||tCLK(1)|
|td(RSSC)||Serial interface reset to first SCLK↑: delay time||TIMEOUT bit =1||4||tCLK|