Reset the ADC by taking the RESET/PWDN pin low for a minimum four fCLK cycles, and then returning the pin high, as shown in Figure 9-53. Holding the RESET/PWDN pin low for longer than 65536 fCLK cycles (9 ms) engages power-down mode. As depicted in the diagram, after the RESET/PWDN pin is taken high, the delay time shown in Table 9-31 is required before sending the first serial interface command.
|th(RSTL)||RESET/PWDN low for reset: hold time||4||tCLK(1)|
|RESET/PWDN low for power down: hold time||65536|
|th(RSTCM)||RESET/PWDN high to serial command: hold time||After reset||8||tCLK|
|RESET/PWDN high to serial command: hold time||After exiting power down||65536|