SBOS998D June   2021  – July 2025 BUF802

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics Wide Bandwidth Mode
    6. 5.6 Electrical Characteristics Low Quiescent Current Mode
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and Output Overvoltage Clamp
      2. 7.3.2 Adjustable Quiescent Current
      3. 7.3.3 ESD Structure
    4. 7.4 Device Functional Modes
      1. 7.4.1 Buffer Mode (BF Mode)
      2. 7.4.2 Composite Loop Mode (CL Mode)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Oscilloscope Front-End Amplifier Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Transforming a Wide-Bandwidth, 50‑Ω Input Signal Chain to High-Input Impedance
        1. 8.2.2.1 Detailed Design Procedure
        2. 8.2.2.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGT|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

BUF802 RGT Package, 16-Pin VQFN(Top View and Bottom View) Figure 4-1 RGT Package, 16-Pin VQFN
(Top View and Bottom View)
Table 4-1 Pin Functions
PIN TYPE(1) OPERATING MODE(2)(3) DESCRIPTION
NAME NO.
Aux_Bias 6 P CL Connect to VS– to enable control of OUT through the In_Aux
CLH 15 I BF, CL Input pin for setting positive clamp voltage
CLL 14 I BF, CL Input pin for setting negative clamp voltage
IN 2 I BF, CL Signal input
In_Aux 4 I CL Auxiliary input for controlling OUT through an external amplifier
In_Bias 3 I CL JFET biasing pin
NC 16, 13, 9 NC — Do not connect
OUT 11 O BF, CL Signal output
R_Bias 7 I BF, CL Output-stage bias-current setting pin
VS+ 1 P BF, CL Positive power supply connection for the input stage
VS– 5, 8 P BF, CL Negative power supply connection for the input stage; pin 5 and pin 8 are internally shorted
VSO+(4) 12 P BF, CL Positive power supply connection for the output stage
VSO–(4) 10 P BF, CL Negative power supply connection for the output stag
Thermal Pad — — The thermal pad is electrically isolated from the die and pins; connect the thermal pad to any potential
(1) I = input, O= output, P= power, NC = no connect.
(2) See Section 7.4 for more information on Buffer Mode (BF) and Composite Loop Mode (CL) functional modes.
(3) Use pins specified as CL only when operating in Composite Loop Mode, and float these pins when operating in Buffer Mode.
(4) Tie VSO and VS to the same potential because these pins are internally connected to the other through back-to-back diodes.