SBOS998D June   2021  – July 2025 BUF802

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics Wide Bandwidth Mode
    6. 5.6 Electrical Characteristics Low Quiescent Current Mode
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and Output Overvoltage Clamp
      2. 7.3.2 Adjustable Quiescent Current
      3. 7.3.3 ESD Structure
    4. 7.4 Device Functional Modes
      1. 7.4.1 Buffer Mode (BF Mode)
      2. 7.4.2 Composite Loop Mode (CL Mode)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Oscilloscope Front-End Amplifier Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Transforming a Wide-Bandwidth, 50‑Ω Input Signal Chain to High-Input Impedance
        1. 8.2.2.1 Detailed Design Procedure
        2. 8.2.2.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGT|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics Low Quiescent Current Mode

at TA = 25°C, VS = ±6 V, RL = 100 Ω || 400 fF, RS = 25 Ω, VOCM = 0 V (mid-supply), CLH and CLL tied to VS+ and VS– respectively, R_Bias = 35.7 kΩ, and low quiescent current mode (unless otherwise specified)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth VOUT = 100 mVPP 2.6 GHz
LSBW Large-signal bandwidth  VOUT = 1 VPP 2 GHz
VOUT = 2 VPP 0.7
Bandwidth for 0.1 dB flatness VOUT = 1 VPP 0.45 GHz
Bandwidth for –1 dB flatness VOUT = 1 VPP 1.4 GHz
SR Slew rate VOUT  = 1.2-V step, VIN slew rate = 13000 V/µs 5500 V/µs
Rise and fall time VOUT  = 1.2-V step (10% to 90%) 0.3 ns
VOUT  = 0.25-V step (10% to 90%) 0.16
Settling time to 0.1% VOUT  = 1.2-V step, VIN slew rate = 13000 V/µs 1.4 ns
Settling time to 1% VOUT  = 1.2-V step, VIN slew rate = 13000 V/µs 0.8
en Voltage noise 1/f corner 10 kHz
f = 100 MHz 2.2 nV/√Hz
in Current noise f = 10 kHz 1.5 fA/√Hz
HD2/HD3 Harmonic distortion VOUT = 2 VPP f = 500 MHz –35/–32 dBc
VOUT = 1 VPP f = 100 MHz –80/–77
f = 500 MHz –56/–54
DC PERFORMANCE
G DC gain VOUT = ±0.5 V RL = 200 Ω  0.96 0.975 0.99 V/V
RL = 100 Ω 0.95 0.963 0.98
VOUT = ±0.5 V,
TA = –40℃ to +85℃		 RL = 200 Ω 0.96 0.99
RL = 100 Ω 0.95 0.98
INPUT
CLH clamping time Time taken to clamp VOUT to VCLH during overdrive 0.3 ns
CLL clamping time Time taken to clamp VOUT to VCLL during overdrive 0.7
OUTPUT
ZO Output impedance f = 100 MHz 1.2 Ω
POWER SUPPLY
IQ Quiescent current IOUT = 0 mA
(R_bias = 35.7 kΩ) 		 21 24 mA
TA = –40℃ to +85℃ 22