SBOS998C June   2021  – March 2022 BUF802

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Wide Bandwidth Mode
    6. 6.6 Electrical Characteristics: Low Quiescent Current Mode
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input and Output Over-Voltage Clamp
      2. 8.3.2 Adjustable Quiescent Current
      3. 8.3.3 ESD Structure
    4. 8.4 Device Functional Modes
      1. 8.4.1 Buffer Mode (BF Mode)
      2. 8.4.2 Composite Loop Mode (CL Mode)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Oscilloscope Front-End Amplifier Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Transforming a Wide-Bandwidth, 50 Ω Input Signal Chain to High-Input Impedance
        1. 9.2.2.1 Detailed Design Results
        2. 9.2.2.2 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.1.2 Detailed Design Procedure

  • Input Impedance: The JFET-input stage of the BUF802 offers giga ohm's of input impedance and therefore enables the front-end to be terminated with a 1 MΩ resistor without affecting performance. A 50 Ω resistance can also be switched in offering matched termination for high-frequency signals. The BUF802 therefore enables the designer to use both 1 MΩ and 50 Ω termination in the same signal chain.
  • Noise: The total noise of the front-end amplifier is the function of the voltage and current noise of the BUF802, OPA140, and the resistors thermal noise. The dominant noise source, however, is contributed by the voltage noise of the BUF802 due to its presence across the complete bandwidth. Thus, the total RMS noise of the front-end amplifier shall be approximately equal to the voltage noise of BUF802 over 1 GHz.

    The specified input referred voltage noise of the BUF802, as shown in Section 6.5, is 2.3 nV/√Hz. The total input referred RMS noise in a bandwidth of 1 GHz is given by the following equation:

    Equation 1. EnRMS = 2.3 nV/√Hz × √ (1 GHz × 1.22) = 80 µVRMS.

    1.22 = Brickwall correction factor. Detailed calculations can be found on TI Precision Labs – Op Amps: Noise – Spectral Density.

    Total input refered spot noise as a function of frequency is shown in Figure 9-3. Assuming the oscilloscope has 8 divisions on the screen and a highest resolution of 1 mV, the full-scale reading is 8 mVPP or 2.82 mVRMS. Thus, the SNR of the front-end amplifier stage at the highest-resolution setting is:

    Equation 2. 20 × log (2.82 mVRMS / 80 µVRMS) = 31 dB.
  • S11 Optimzation: The front-end amplifier circuit should have a perfect 50 Ω termination to achieve the required S11 parameter of -15 dB across the frequency. While it is possible to mount an exact 50 Ω resistance at the input of the front-end composite loop circuit, the parasitic capacitance of the BUF802 appears in parallel to this 50 Ω resistance resulting in a net imperfect termination.

    The parasitic input capacitance of BUF802 (IN pin) is 2.4 pF. At 1 GHz this parasitic capacitance reduces down to an impedance of 66.3 Ω. Thus, the net input impedance as seen by the signal at the input is the following:

    Equation 3. 66.3 Ω || 50 Ω = 28.5 Ω
    This results in an imperfect termination for the 50 Ω source resulting in poor S11. The addition of a 30 Ω resistance in series with the input trace and a 6.8 nH inductor in series with the onboard 50 Ω termination helps isolate the input parasitic capacitance as well as ensures the net input impedance is maintained at 50 Ω. The S11 response of this modified circuit is shown in Figure 9-4.

    Figure 9-2 Net Input Impedance
  • Uniform Gain Across Frequency: The front-end amplifier circuit is designed with BUF802 and OPA140 connected in a composite loop. The loop splits the input signal into low- and high-frequency components, taking both components to the output through two different circuits (transfer functions) and recombining them to reproduce a net output signal. The end goal is to achieve a smooth transition between the two circuits and ensure a flat frequency response from DC till the frequency of interest.

    CL Mode of BUF802 simplifies this design for achieving a flat frequency response from DC till the frequency of interest (1 GHz in this case). To achieve a flat response, the following two conditions have to be met:

    1. α/β = G
    2. High frequency response pole fHF<< low frequency pole fLF

    α is the input attenuation factor and β is the inverse of the non-inverting gain of the precision amplifier. G is the DC gain of the Main Path of the BUF802. Since G can vary from device-to-device, trimming either α or β is recommended to achieve a flat frequency response. In Figure 9-1, β may be trimmed using the RPOT. Since G is ≈1 V/V and α is 1/5 (200 kΩ / (200 kΩ + 800 kΩ)), RPOT should be trimmed so that β ≈ 1/5.

    For the β network, it is recommended to use resistors which are an order of magnitude of resistance lower than the resistors used in the α network. Therefore β resistor values of 80 kΩ and ≈20 kΩ have been chosen.

    fHF is the pole resulting from the 330 pF series capacitor and the 10 MΩ resistor on the In_Bias pin.

    Equation 4. fHF = 1/(2 × pi × R × C) = 1/(2 × 3.14 × 10 MΩ × 330 pF) = 48 Hz

    fLF is the pole resulting from the gain bandwidth of the precision amplifier (OPA140), the Auxiliary Path bandwidth and other parasitic capacitance of the resistor network.

    Equation 5. fLF = GBW × GAUX × β = 440 kHz

    Where GBW is the gain bandwidth product of the precision amplifier (OPA140) = 11 MHz. GAUX is the gain from In_Aux to OUT = 0.2 V/V. 1/β is the external non-inverting gain set for the precision amplifier = 5 V/V.

    Based on the above value of fHF and fLF, the required condition of fHF<< fLF is met. CF, connected across the precision amplifier, is required to compensate for the parasitic capacitance and to make the overall poles and zeros cancel each other. The value of CF can be found by using the following equation:

    Equation 6. CF = CINPA × ((G × Rα2 / Rβ2) – 1)).

    Where CINPA is the common mode input capacitance of the precision amplifier, OPA140 in this case.

    Plugging in the value of these components arrives at CF = 56 pF. In the final system, based on the quality of the flat band response needed, CF may or may not be trimmed along with RPOT in the final production flow.