SBOS998D June   2021  – July 2025 BUF802

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics Wide Bandwidth Mode
    6. 5.6 Electrical Characteristics Low Quiescent Current Mode
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and Output Overvoltage Clamp
      2. 7.3.2 Adjustable Quiescent Current
      3. 7.3.3 ESD Structure
    4. 7.4 Device Functional Modes
      1. 7.4.1 Buffer Mode (BF Mode)
      2. 7.4.2 Composite Loop Mode (CL Mode)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Oscilloscope Front-End Amplifier Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Transforming a Wide-Bandwidth, 50‑Ω Input Signal Chain to High-Input Impedance
        1. 8.2.2.1 Detailed Design Procedure
        2. 8.2.2.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGT|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Input and Output Overvoltage Clamp

BUF802 Internal Input and Output Overvoltage Clamp Figure 7-1 Internal Input and Output Overvoltage Clamp

The BUF802 device integrates an input and output clamp circuit. The input clamp protects the BUF802 from large input transients and the output clamp protects the subsequent stages from being overdriven.

  • Input Clamp Circuit:
    • Figure 7-1 shows the input of the BUF802 tied to pins CLH and VS- through two internal clamp diodes, D1 and D2. The diodes are rated for 100 mA of continuous current but withstand much higher transient currents. If the JFET input voltage exceeds the voltage at CLH or VS–, the diodes get forward biased, clamping the JFET to CLH and VS-. A 1‑μF capacitor connected in parallel to the zener diode helps in transient absorption traveling through the D1 diode.
    • Figure 7-2 shows how the external clamping diodes is used in cases where the 100‑mA current rating of D1 and D2 is insufficient. When using external clamping, disable the internal protection of the BUF802 by connecting CLH and CLL to VS+ and VS–.
BUF802 External Input Clamp Circuit Figure 7-2 External Input Clamp Circuit
  • Output Clamp Circuit:
    • The output protection circuit prevents the stages following the BUF802 from being overdriven. This circuit also helps the BUF802 recover rapidly from a saturated state resulting from an input- or output-overdrive condition. In a typical data-acquisition system, the BUF802 is followed by a variable gain amplifier (VGA). High-speed VGAs are typically designed on 5‑V processes, making the device susceptible to potential damage from the 12‑V BUF802. The voltage applied to the CLH and CLL pins dictate the maximum output swing of the BUF802.
    • Figure 7-2 shows that the internal clamps are disabled by connecting CLH and CLL to VS+ and VS–, respectively. When the clamps are disabled, the maximum output swing is limited by the output swing specification described in Section 5.5. Section 5.7 shows the response time and accuracy of the output clamp.
    • The output THD of the BUF802 degrades when VCLH and VCLL are set close to the expected VOUT peak value. To prevent signal degradation, maintain at least a 1.5-V difference between the expected peak output voltage and the clamp voltage applied at the CLH and CLL pins. Figure 7-3 shows the relation between the absolute clamp voltage value and THD for a 1 VPP output.
BUF802 THD vs VCLH / VCLL for VOUT = 1 VPPFigure 7-3 THD vs VCLH / VCLL for VOUT = 1 VPP
BUF802 Transient Clamp ResponseFigure 7-4 Transient Clamp Response