SBOS998D June   2021  – July 2025 BUF802

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics Wide Bandwidth Mode
    6. 5.6 Electrical Characteristics Low Quiescent Current Mode
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and Output Overvoltage Clamp
      2. 7.3.2 Adjustable Quiescent Current
      3. 7.3.3 ESD Structure
    4. 7.4 Device Functional Modes
      1. 7.4.1 Buffer Mode (BF Mode)
      2. 7.4.2 Composite Loop Mode (CL Mode)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Oscilloscope Front-End Amplifier Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Transforming a Wide-Bandwidth, 50‑Ω Input Signal Chain to High-Input Impedance
        1. 8.2.2.1 Detailed Design Procedure
        2. 8.2.2.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGT|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics Wide Bandwidth Mode

at TA = 25°C, VS = ±6 V, RL = 100 Ω || 400 fF, RS = 25 Ω, VOCM = 0 V (mid-supply), CLH and CLL tied to VS+ and VS– respectively, R_Bias = 17.8 kΩ, and wide bandwidth mode (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth VOUT = 100 mVPP 3.1 GHz
LSBW Large-signal bandwidth  VOUT = 1 VPP 3.1 GHz
VOUT = 2 VPP 1.6
Bandwidth for 0.1-dB flatness VOUT = 1 VPP, RL = 100 Ω 0.6 GHz
Bandwidth for −1-dB flatness VOUT = 1 VPP, RL = 100 Ω 1.8 GHz
Bandwidth for −2-dB flatness VOUT = 1 VPP, RL = 50 Ω 2.4 GHz
SR Slew rate VOUT = 1.2-V step, VIN slew rate = 13000 V/µs 7000 V/µs
Rise and fall time VOUT = 1.2-V step (10% to 90%) 0.16 ns
VOUT = 0.25-V step (10% to 90%) 0.15
Settling time to 0.1% VOUT = 1.2-V step, VIN slew rate = 13000 V/µs 1.3 ns
Settling time to 1% VOUT = 1.2-V step, VIN slew rate = 13000 V/µs 0.7 ns
en Voltage noise 1/f corner 18 kHz
f = 100 MHz in BF mode and CL mode 2.3 nV/√Hz
in Current noise f = 10 kHz 1.5 fA/√Hz
HD2/HD3 Harmonic distortion VOUT = 2 VPP f = 500 MHz –68/–58 dBc
VOUT = 1 VPP f = 1 GHz –55/–59
f = 2 GHz –45/–49
f = 2 GHz, RL = 50 Ω –43/–41
DC PERFORMANCE
VOS Input offset voltage VOUT – VIN –600 –800 mV
TA = –40℃ to +85℃ –900
dVOS/dT Input offset voltage drift TA = –40℃ to +85℃ ±700 ±1330 µV/℃
IB Input bias current 3 25 pA
TA = –40℃ to +85℃ 220
IAB Auxiliary input bias current 44 140 µA
TA = –40℃ to +85℃ 200
G DC gain VOUT = ± 0.5 V RL = 200 Ω  0.97 0.978 0.99 V/V
RL = 100 Ω 0.96 0.971 0.98
RL = 50 Ω 0.95 0.961 0.97
VOUT = ± 0.5 V,
TA = –40℃ to +85℃		 RL = 200 Ω 0.97 0.99
RL = 100 Ω 0.96 0.98
RL = 50 Ω 0.94 0.97
INPUT
ZIN Input impedance f = 100 MHz  50 || 2.4 GΩ || pF
Input clamp current rating Continuous current rating 100 mA
VCLH High side clamp voltage(1) 0 VS+ V
VCLL Low side clamp voltage(1) VS– 0
CLH clamping time Time taken to clamp VOUT to VCLH during overdrive 0.2 ns
CLL clamping time Time taken to clamp VOUT to VCLL during overdrive 0.2
Input voltage  THD = –40 dBc f = 500 MHz 4.5 VPP
f = 1 GHz 2.1
f = 2 GHz 1.2
OUTPUT
Output swing TA = 25℃ VS+ – 1.9 VS– + 3.4 V
TA = –40℃ to +85℃ VS+ – 2.0 VS– + 3.4
ZO Output impedance f = 100 MHz 1.2 Ω
AUXILIARY INPUT
GAUX VOUT / In_Aux gain At low frequency (VIN is left floating)  6.15 20 V/V
At crossover frequency (VIN shorted to GND)  0.18 0.26
Default voltage at In_Aux Driving In_Aux to default voltage
results in VOUT = mid-supply		 VS– + 2.3 VS– + 3 VS– + 3.8 V
In_Aux input voltage  At crossover frequency  VS– + 1.0 VS– + 5.0 V
GAUX BW VOUT / In_Aux  bandwidth  800 MHz
RHF Resistance between In_Bias to JFET source 100 kΩ
POWER SUPPLY
IQ Quiescent current IOUT = 0 mA
(R_bias = 17.8 kΩ) 		 34 37 mA
TA = –40℃ to +85℃ 35.5
CL Mode enabled 36 40
PSRR Power-supply rejection ratio PSRR at 100 kHz on VS+ 49 dB
PSRR at 100 kHz on VS– 38
(1) The 0-V limits are for bipolar and balanced power supplies. For other supply configurations mid-supply sets the minimum limit for VCLH and maximum limit for VCLL.