SBASAO8A June   2025  – April 2026 DAC39RF20

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI Interface Timing Diagrams
    11. 6.11 Typical Characteristics: DC Linearity, Output Power and Crosstalk
    12. 6.12 Typical Characteristics: Single Tone Spectra
    13. 6.13 Typical Characteristics: Phase, Amplitude Noise and Clock Delays
    14. 6.14 Typical Characteristics: Single Tone Linearity
    15. 6.15 Typical Characteristics: Power and Supply Currents
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RF Mode
        3. 7.3.1.3 DES Modes
      2. 7.3.2  DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3  DEM and Dither
      4. 7.3.4  Offset Adjustment
      5. 7.3.5  Clocking Subsystem
        1. 7.3.5.1 Converter Phase Locked Loop (CPLL)
        2. 7.3.5.2 Clock and SYSREF Delay
        3. 7.3.5.3 SYSREF Capture and Monitoring
          1. 7.3.5.3.1 SYSREF Frequency Requirements
          2. 7.3.5.3.2 SYSREF Pulses for Full Alignment
          3. 7.3.5.3.3 Automatic SYSREF Calibration and Tracking
            1. 7.3.5.3.3.1 SYSREF Automatic Calibration Procedure
            2. 7.3.5.3.3.2 Multi-device Alignment
            3. 7.3.5.3.3.3 Calibration Failure
            4. 7.3.5.3.3.4 SYSREF Tracking
        4. 7.3.5.4 Trigger Clocking
      6. 7.3.6  Digital Signal Processing Blocks
        1. 7.3.6.1  Bypass Mode
        2. 7.3.6.2  DUC Mode
          1. 7.3.6.2.1 Digital Upconverter (DUC)
            1. 7.3.6.2.1.1 Interpolation Filters
            2. 7.3.6.2.1.2 Numerically Controlled Oscillator (NCO)
              1. 7.3.6.2.1.2.1 Phase-continuous NCO Update Mode
              2. 7.3.6.2.1.2.2 Phase-coherent NCO Update Mode
              3. 7.3.6.2.1.2.3 Phase-sync NCO Update Mode
              4. 7.3.6.2.1.2.4 NCO Synchronization
                1. 7.3.6.2.1.2.4.1 JESD204C LSB Synchronization
        3. 7.3.6.3  DDS SPI Mode
        4. 7.3.6.4  DDS Vector Mode
          1. 7.3.6.4.1 Second Order Amplitude Support
          2. 7.3.6.4.2 Vector Order and Symmetric Vector Mode
          3. 7.3.6.4.3 Initial Startup
          4. 7.3.6.4.4 Trigger Queuing
          5. 7.3.6.4.5 Trigger Burst
          6. 7.3.6.4.6 Hold Mode
          7. 7.3.6.4.7 Indexing Mode
          8. 7.3.6.4.8 Queued or Burst Triggers in Indexing-Mode
          9. 7.3.6.4.9 Writing Vectors While DDS is Enabled
        5. 7.3.6.5  DDS Streaming Mode
        6. 7.3.6.6  DSP Triggering
          1. 7.3.6.6.1 Trigger Latency
        7. 7.3.6.7  NCO Square Wave Mode
          1. 7.3.6.7.1 Square Wave Enable
        8. 7.3.6.8  DSP Mute Function
        9. 7.3.6.9  DSP Output Gain
        10. 7.3.6.10 Complex Output Support
        11. 7.3.6.11 Channel Bonder
        12. 7.3.6.12 Programmable FIR Filter
          1. 7.3.6.12.1 PFIR Coefficients
          2. 7.3.6.12.2 PFIR Reflection Cancellation Mode
          3. 7.3.6.12.3 PFIR Power Savings
          4. 7.3.6.12.4 PFIR Usage
        13. 7.3.6.13 DES Interpolator
          1. 7.3.6.13.1 DAC Mute Function
      7. 7.3.7  Serdes Physical Layer
        1. 7.3.7.1 Serdes PLL
          1. 7.3.7.1.1 Enabling the Serdes PLL
          2. 7.3.7.1.2 Reference Clock
          3. 7.3.7.1.3 PLL VCO Calibration
          4. 7.3.7.1.4 Serdes PLL Loop Bandwidth
        2. 7.3.7.2 Serdes Receiver
          1. 7.3.7.2.1 Serdes Data Rate Selection
          2. 7.3.7.2.2 Serdes Receiver Termination
          3. 7.3.7.2.3 Serdes Receiver Polarity
          4. 7.3.7.2.4 Serdes Clock Data Recovery
          5. 7.3.7.2.5 Serdes Equalizer
            1. 7.3.7.2.5.1 Adaptive Equalization
            2. 7.3.7.2.5.2 Fixed Equalization
            3. 7.3.7.2.5.3 Pre and Post Cursor Analysis
          6. 7.3.7.2.6 Serdes Receiver Eyescan
            1. 7.3.7.2.6.1 Eyescan Procedure
            2. 7.3.7.2.6.2 Building an Eye Diagram
        3. 7.3.7.3 Serdes PHY Status
      8. 7.3.8  JESD204C Interface
        1. 7.3.8.1 Deviation from JESD204C Standard
        2. 7.3.8.2 Link Layer
          1. 7.3.8.2.1 Serdes Crossbar
          2. 7.3.8.2.2 Bit Error Rate Tester
          3. 7.3.8.2.3 Scrambler and Descrambler
          4. 7.3.8.2.4 64b and 66b Decoding Link Layer
            1. 7.3.8.2.4.1 Sync Header Alignment
            2. 7.3.8.2.4.2 Extended Multiblock Alignment
            3. 7.3.8.2.4.3 Data Integrity
          5. 7.3.8.2.5 8B and 10B Encoding Link Layer
            1. 7.3.8.2.5.1 Code Group Synchronization (CGS)
            2. 7.3.8.2.5.2 Initial Lane Alignment Sequence (ILAS)
            3. 7.3.8.2.5.3 Multi-frames and the Local Multiframe Clock (LMFC)
            4. 7.3.8.2.5.4 Frame and Multiframe Monitoring
            5. 7.3.8.2.5.5 Link Restart
            6. 7.3.8.2.5.6 Link Error Reports
            7. 7.3.8.2.5.7 Watchdog Timer (JTIMER)
        3. 7.3.8.3 SYSREF Alignment Required in Subclass 1 Mode
        4. 7.3.8.4 Transport Layer
        5. 7.3.8.5 JESD204C Debug Capture (JCAP)
          1. 7.3.8.5.1 Physical Layer Debug Capture
          2. 7.3.8.5.2 Link Layer Debug Capture
          3. 7.3.8.5.3 Transport Layer Debug Capture
        6. 7.3.8.6 JESD204C Interface Modes
          1. 7.3.8.6.1 JESD204C Format Diagrams
            1. 7.3.8.6.1.1 16-bit Formats
            2. 7.3.8.6.1.2 12-bit Formats
            3. 7.3.8.6.1.3 8-bit Formats
          2. 7.3.8.6.2 DUC and DDS Modes
      9. 7.3.9  Data Path Latency
      10. 7.3.10 Multi-Device Synchronization and Deterministic Latency
        1. 7.3.10.1 Programming RBD
        2. 7.3.10.2 Multiframe Lengths less than 32 Octa-Bytes (256 Bytes)
        3. 7.3.10.3 Recommended Algorithm to Determine the RBD Value
        4. 7.3.10.4 Operation in Subclass 0 Systems
      11. 7.3.11 Link Reset
      12. 7.3.12 Alarm Generation
        1. 7.3.12.1 Over Range Detection
        2. 7.3.12.2 Over Range Masking
      13. 7.3.13 Mute Function
        1. 7.3.13.1 Alarm Data Path Muting
        2. 7.3.13.2 Transmit Enables
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
    5. 7.5 Programming
      1. 7.5.1 Using the Standard SPI Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Protocol
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 Using the Fast Reconfiguration Interface
  9. 8 Register Maps
    1. 8.1  Standard_SPI-3.1 Registers
    2. 8.2  System Registers
    3. 8.3  Trigger Registers
    4. 8.4  CPLL_AND_CLOCK Registers
    5. 8.5  SYSREF Registers
    6. 8.6  JESD204C Registers
    7. 8.7  JESD204C_Advanced Registers
    8. 8.8  SerDes_Equalizer Registers
    9. 8.9  SerDes_Eye-Scan Registers
    10. 8.10 SerDes_Lane_Status Registers
    11. 8.11 SerDes_PLL Registers
    12. 8.12 DAC_and_Analog_Configuration Registers
    13. 8.13 Datapath Registers
    14. 8.14 NCO_and_Mixer Registers
    15. 8.15 Alarm Registers
    16. 8.16 Fuse_Control Registers
    17. 8.17 Fuse_Backed Registers
    18. 8.18 DDS_Vector_Mode Registers
    19. 8.19 Programmable_FIR Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Startup Procedure
      2. 9.1.2 Bandwidth Optimization for Square Wave Mode
    2. 9.2 Typical Application: Ku-Band Radar Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up and Down Sequence
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.3.6.2.1.1 Interpolation Filters

The first operation of the DUC is to interpolate the input signal to a higher data rate. The available interpolation options are summarized in Table 7-7. The sampling rate of the input signal is multiplied by the specified interpolation amount to determine the DAC output rate, subject to the maximum sample rate for the DAC39RF20. These rates do not include the optional 2x interpolation for DES mode. For interpolations rates 6x and below, a reduced number of DUC channels are available.

Table 7-7 Summary of Interpolation Options
INTERPOLATIONMaximum Number of DUC channels
4x2 (only DUC0 and DUC1)
6x2 (only DUC0 and DUC1)
8x4
12x4
16x4
24x4
32x4
48x4
64x4
96x4
128x4
192x4
256x4

Each DUC contains multiple 2x or 3x interpolating filters. The composite interpolation filter responses are given in Figure 7-11 to Figure 7-35. The filters are designed to provide a passband bandwidth of 81.4% on the input bandwidth and passband ripple less than 0.001dB. The stopband attenuation is greater than 90dB for any signal within the passband.

DAC39RF20 4x Interpolation Filter ResponseFigure 7-11 4x Interpolation Filter Response
DAC39RF20 6x Interpolation Filter ResponseFigure 7-13 6x Interpolation Filter Response
DAC39RF20 8x Interpolation Filter ResponseFigure 7-15 8x Interpolation Filter Response
DAC39RF20 12x Interpolation Filter ResponseFigure 7-17 12x Interpolation Filter Response
DAC39RF20 16x Interpolation Filter ResponseFigure 7-19 16x Interpolation Filter Response
DAC39RF20 24x Interpolation Filter ResponseFigure 7-21 24x Interpolation Filter Response
DAC39RF20 32x Interpolation Filter ResponseFigure 7-23 32x Interpolation Filter Response
DAC39RF20 48x Interpolation Filter ResponseFigure 7-25 48x Interpolation Filter Response
DAC39RF20 64x Interpolation Filter ResponseFigure 7-27 64x Interpolation Filter Response
DAC39RF20 96x Interpolation Filter ResponseFigure 7-29 96x Interpolation Filter Response
DAC39RF20 128x Interpolation Filter ResponseFigure 7-31 128x Interpolation Filter Response
DAC39RF20 192x Interpolation Filter ResponseFigure 7-33 192x Interpolation Filter Response
DAC39RF20 256x Interpolation Filter ResponseFigure 7-35 256x Interpolation Filter Response
DAC39RF20 4x Interpolation Filter Passband ResponseFigure 7-12 4x Interpolation Filter Passband Response
DAC39RF20 6x Interpolation Filter Passband ResponseFigure 7-14 6x Interpolation Filter Passband Response
DAC39RF20 8x Interpolation Filter Passband ResponseFigure 7-16 8x Interpolation Filter Passband Response
DAC39RF20 12x Interpolation Filter Passband ResponseFigure 7-18 12x Interpolation Filter Passband Response
DAC39RF20 16x Interpolation Filter Passband ResponseFigure 7-20 16x Interpolation Filter Passband Response
DAC39RF20 24x Interpolation Filter Passband ResponseFigure 7-22 24x Interpolation Filter Passband Response
DAC39RF20 32x Interpolation Filter Passband ResponseFigure 7-24 32x Interpolation Filter Passband Response
DAC39RF20 48x Interpolation Filter Passband ResponseFigure 7-26 48x Interpolation Filter Passband Response
DAC39RF20 64x Interpolation Filter Passband ResponseFigure 7-28 64x Interpolation Filter Passband Response
DAC39RF20 96x Interpolation Filter Passband ResponseFigure 7-30 96x Interpolation Filter Passband Response
DAC39RF20 128x Interpolation Filter Passband ResponseFigure 7-32 128x Interpolation Filter Passband Response
DAC39RF20 192x Interpolation Filter Passband ResponseFigure 7-34 192x Interpolation Filter Passband Response
DAC39RF20 256x Interpolation Filter Passband ResponseFigure 7-36 256x Interpolation Filter Passband Response