DLPS206 May   2021 DLPC7540

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  DMD HSSI Electrical Characteristics
    8. 6.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 6.9  V-by-One Interface Electrical Characteristics
    10. 6.10 FPD-Link LVDS Electrical Characteristics
    11. 6.11 USB Electrical Characteristics
    12. 6.12 System Oscillator Timing Requirements
    13. 6.13 Power Supply and Reset Timing Requirements
    14. 6.14 DMD HSSI Timing Requirements
    15. 6.15 DMD Low-Speed LVDS Timing Requirements
    16. 6.16 V-by-One Interface General Timing Requirements
    17. 6.17 FPD-Link Interface General Timing Requirements
    18. 6.18 Source Frame Timing Requirements
    19. 6.19 Synchronous Serial Port Interface Timing Requirements
    20. 6.20 Master and Slave I2C Interface Timing Requirements
    21. 6.21 Programmable Output Clock Timing Requirements
    22. 6.22 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    23. 6.23 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    24. 6.24 Multi-Trace ETM Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 Processing Delays
      3. 7.3.3 FPD-Link Interface
      4. 7.3.4 V-by-One interface
      5. 7.3.5 DMD (HSSI) Interface
      6. 7.3.6 Program Memory Flash Interface
      7. 7.3.7 GPIO Supported Functionality
      8. 7.3.8 Debug Support
    4. 7.4 Device Operational Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
        2. 7.4.2.2 Low Latency Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Management
    2. 9.2 Hot Plug Usage
    3. 9.3 Power Supplies for Unused Input Source Interfaces
    4. 9.4 Power Supplies
      1. 9.4.1 1.15-V Power Supplies
      2. 9.4.2 1.21V Power Supply
      3. 9.4.3 1.8-V Power Supplies
      4. 9.4.4 3.3-V Power Supplies
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Layout Guidelines
      2. 10.1.2  Power Supply Layout Guidelines
      3. 10.1.3  Layout Guidelines for Internal Controller PLL Power
      4. 10.1.4  Layout Guideline for DLPC7540 Reference Clock
        1. 10.1.4.1 Recommended Crystal Oscillator Configuration
      5. 10.1.5  V-by-One Interface Layout Considerations
      6. 10.1.6  FPD-Link Interface Layout Considerations
      7. 10.1.7  USB Interface Layout Considerations
      8. 10.1.8  DMD Interface Layout Considerations
      9. 10.1.9  General Handling Guidelines for Unused CMOS-Type Pins
      10. 10.1.10 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 10.2 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
        2. 11.1.2.2 Package Data
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
      1. 11.4.1 Video Timing Parameter Definitions
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1.4.1 Recommended Crystal Oscillator Configuration

Table 10-2 Recommended Crystal Configurations
PARAMETERCRYSTAL ACRYSTAL BUNIT
Crystal circuit configurationParallel resonantParallel resonant
Crystal typeFundamental (first harmonic)Fundamental (first harmonic)
Crystal nominal frequency4038MHz
Crystal frequency tolerance (1)±100 (200 p-p max)±100 (200 p-p max)PPM
Crystal equivalent series resistance (ESR)60 (Max)60 (Max)Ω
Crystal load capacitance20 (Max)20 (Max)pF
Crystal Shunt Load capacitance7 (Max)7 (Max)pF
Temperature range-40°C to +85°C-40°C to +85°C°C
Drive level100 (Nominal)100 (Nominal)µW
RFB feedback resistor (nominal)1Meg (Nominal)1Meg (Nominal)Ω
CL1 external crystal load capacitorSee equation in (2)See equation in (2)pF
CL2 external crystal load capacitorSee equation in (3)See equation in (3)(3)pF
PCB layoutA ground isolation ring around the crystal is recommendedA ground isolation ring around the crystal is recommended
(1) Crystal frequency tolerance to include accuracy, temperature, aging, and trim sensitivity. These are typically specified separately and the sum of all required to meet this requirement.
(2) CL1 = 2 × (CL – Cstray_pll_refclk_i), where: Cstray_pll_refclk_i = Sum of package and PCB stray capacitance at the crystal pin associated with the Controller pin REFCLKx_I. See Table 10-3.
(3) CL2 = 2 × (CL – Cstray_pll_refclk_o), where: Cstray_pll_refclk_o = Sum of package and PCB stray capacitance at the crystal pin associated with the Controller pin REFCLKx_O. See Table 10-3.
Table 10-3 Crystal Pin Capacitance
PARAMETER MIN NOM MAX Units
Cstray_pll_refclkA_i Sum of package and PCB stray capacitance at REFCLKA_I 4.5 pF
Cstray_pll_refclkA_o Sum of package and PCB stray capacitance at REFCLKA_O 4.5 pF
Cstray_pll_refclkB_i Sum of package and PCB stray capacitance at REFCLKB_I 4.5 pF
Cstray_pll_refclkB_o Sum of package and PCB stray capacitance at REFCLKB_O 4.5 pF

The crystal circuits in the DLPC7540 have dedicated power (VAD33_OSCA and VAD33_OSCB) pins, with the recommended filtering for each shown in Figure 10-11, and recommended values shown in Table 10-1

GUID-6AD3ABB7-DC24-4922-9D7F-4EB3DA9EBD72-low.gifFigure 10-11 Crystal Power Supply Filtering
Table 10-4 DLPC7540 Recommended Crystal Parts
MANUFACTURERPART NUMBERNOMINAL FREQUENCYFREQUENCY TOLERANCE,
FREQUENCY STABILITY,
AGING/YEAR		ESRLOAD CAPACITANCEOPERATING TEMPERATUREDrive Level
TXC7M38070001 (1)38 MHzFreq Tolerance:
±20 ppm		30Ω max12 pF–40°C to +85°C100µW
Freq Stability:
±20 ppm
Aging/Year: ±3 ppm
TXC7M40070041 (2)40 MHzFreq Tolerance:
±20 ppm		30Ω max12 pF–40°C to +85°C100µW
Freq Stability:
±20 ppm
Aging/Year: ±3 ppm
(1) This device requires an RS resistor with value = 0.
(2) This device requires an RS resistor with value = 0.