DLPS206 May 2021 DLPC7540
PRODUCTION DATA
The DLPC7540 Controller supports a single 8 lane V-by-One port which can be configured for 1, 2, 4 or 8 lane use. This interface supports limited lane remapping which is shown in . Intra-lane remapping (i.e. swapping P with N) is not supported.
Independent from the remapping of the physical V-by-One interface, the DLPC7540 supports a number of data mappings onto the actual physical interface as specified by the standard. V-by-One sources must match at least one of these mappings These are shown in Table 7-8, Table 7-9, Table 7-10, Table 7-11, Table 7-12, Table 7-13, Table 7-14, Table 7-15, Table 7-16, and Table 7-17.
V-by-One Data Map Mode 0 | |||
---|---|---|---|
V-by-One Input Data Bit | 36bpp RGB/YCbCr 4:4:4 (1) | 30bpp RGB/YCbCr 4:4:4 | Mapper Output |
D[0] | R/Cr[4] | R/Cr[2] | B(2) |
D[1] | R/Cr[5] | R/Cr[3] | B(3) |
D[2] | R/Cr[6] | R/Cr[4] | B(4) |
D[3] | R/Cr[7] | R/Cr(5] | B(5) |
D[4] | R/Cr[8] | R/Cr[6] | B(6) |
D[5] | R/Cr[9] | R/Cr[7] | B(7) |
D[6] | R/Cr[10] | R/Cr[8] | B(8) |
D[7] | R/Cr[11] | R/Cr[9] | B(9) |
D[8] | G/Y[4] | G/Y[2] | A(2) |
D[9] | G/Y[5] | G/Y[3] | A(3) |
D[10] | G/Y[6] | G/Y[4] | A(4) |
D[11] | G/Y[7] | G/Y[5] | A(5) |
D[12] | G/Y[8] | G/Y[6] | A(6) |
D[13] | G/Y[9] | G/Y[7] | A(7) |
D[14] | G/Y[10] | G/Y[8] | A(8) |
D[15] | G/Y[11] | G/Y[9] | A(9) |
D[16] | B/Cb[4] | B/Cb[2] | C(2) |
D[17] | B/Cb[5] | B/Cb[3] | C(3) |
D[18] | B/Cb[6] | B/Cb[4] | C(4) |
D[19] | B/Cb[7] | B/Cb[5] | C(5) |
D[20] | B/Cb[8] | B/Cb[6] | C(6) |
D[21] | B/Cb[9] | B/Cb[7] | C(7) |
D[22] | B/Cb[10] | B/Cb[8] | C(8) |
D[23] | B/Cb[11] | B/Cb[9] | C(9) |
D[24] | |||
D[25] | |||
D[26] | B/Cb[2] | B/Cb[1] | C[0] |
D[27] | B/Cb[3] | B/Cb[0] | C[1] |
D[28] | G/Y[2] | G/Y[1] | A[0] |
D[29] | G/Y[3] | G/Y[0] | A[1] |
D[30] | R/Cr[2] | R/Cr[1] | B[0] |
D[31] | R/Cr[3] | R/Cr[0] | B[1] |
V-by-One Data Map Mode 1 | ||
---|---|---|
V-by-One Input Data Bit | 27bpp RGB/YCbCr 4:4:4 (1) | Mapper Output |
D[0] | R/Cr[1] | B(2) |
D[1] | R/Cr[2] | B(3) |
D[2] | R/Cr[3] | B(4) |
D[3] | R/Cr[4] | B(5) |
D[4] | R/Cr[5] | B(6) |
D[5] | R/Cr[6] | B(7) |
D[6] | R/Cr[7] | B(8) |
D[7] | R/Cr[8] | B(9) |
D[8] | G/Y[1] | A(2) |
D[9] | G/Y[2] | A(3) |
D[10] | G/Y[3] | A(4) |
D[11] | G/Y[4] | A(5) |
D[12] | G/Y[5] | A(6) |
D[13] | G/Y[6] | A(7) |
D[14] | G/Y[7] | A(8) |
D[15] | G/Y[8] | A(9) |
D[16] | B/Cb[1] | C(2) |
D[17] | B/Cb[2] | C(3) |
D[18] | B/Cb[3] | C(4) |
D[19] | B/Cb[4] | C(5) |
D[20] | B/Cb[5] | C(6) |
D[21] | B/Cb[6] | C(7) |
D[22] | B/Cb[7] | C(8) |
D[23] | B/Cb[8] | C(9) |
D[24] | ||
D[25] | ||
'0' | - | C[0] |
D[27] | B/Cb[0] | C[1] |
'0' | - | A[0] |
D[29] | G/Y[0] | A[1] |
'0' | - | B[0] |
D[31] | R/Cr[0] | B[1] |
V-by-One Data Map Mode 2 | ||
---|---|---|
V-by-One Input Data Bit | 24bpp RGB/YCbCr 4:4:4 (1) | Mapper Output |
D[0] | R/Cr[0] | B(2) |
D[1] | R/Cr[1] | B(3) |
D[2] | R/Cr[2] | B(4) |
D[3] | R/Cr[3] | B(5) |
D[4] | R/Cr[4] | B(6) |
D[5] | R/Cr[5] | B(7) |
D[6] | R/Cr[6] | B(8) |
D[7] | R/Cr[7] | B(9) |
D[8] | G/Y[0] | A(2) |
D[9] | G/Y[1] | A(3) |
D[10] | G/Y[2] | A(4) |
D[11] | G/Y[3] | A(5) |
D[12] | G/Y[4] | A(6) |
D[13] | G/Y[5] | A(7) |
D[14] | G/Y[6] | A(8) |
D[15] | G/Y[7] | A(9) |
D[16] | B/Cb[0] | C(2) |
D[17] | B/Cb[1] | C(3) |
D[18] | B/Cb[2] | C(4) |
D[19] | B/Cb[3] | C(5) |
D[20] | B/Cb[4] | C(6) |
D[21] | B/Cb[5] | C(7) |
D[22] | B/Cb[6] | C(8) |
D[23] | B/Cb[7] | C(9) |
D[24] | ||
D[25] | ||
'0' | - | C[0] |
'0' | - | C[1] |
'0' | - | A[0] |
'0' | - | A[1] |
'0' | - | B[0] |
'0' | - | B[1] |
V-by-One Data Map Mode 3 | ||||
---|---|---|---|---|
V-by-One Input Data Bit | 32bpp YCbCr 4:2:2 (2) | 24bpp YCbCr 4:2:2 (3) | 20bpp YCbCr 4:2:2 | Mapper Output |
D[0] | CbCr[8] | CbCr[4] | CbCr[2] | B(2) |
D[1] | CbCr[9] | CbCr[5] | CbCr[3] | B(3) |
D[2] | CbCr[10] | CbCr[6] | CbCr[4] | B(4) |
D[3] | CbCr[11] | CbCr[7] | CbCr[5] | B(5) |
D[4] | CbCr[12] | CbCr[8] | CbCr[6] | B(6) |
D[5] | CbCr[13] | CbCr[8] | CbCr[7] | B(7) |
D[6] | CbCr[14] | CbCr[10] | CbCr[8] | B(8) |
D[7] | CbCr[15] | CbCr[11] | CbCr[9] | B(9) |
D[8] | Y[8] | Y[4] | Y[2] | A(2) |
D[9] | Y[9] | Y[5] | Y[3] | A(3) |
D[10] | Y[10] | Y[6] | Y[4] | A(4) |
D[11] | Y[11] | Y[7] | Y[5] | A(5) |
D[12] | Y[12] | Y[8] | Y[6] | A(6) |
D[13] | Y[13] | Y[9] | Y[7] | A(7) |
D[14] | Y[14] | Y[10] | Y[8] | A(8) |
D[15] | Y[15] | Y[11] | Y[9] | A(9) |
'0' | - | - | - | C(2) |
'0' | - | - | - | C(3) |
'0' | - | - | - | C(4) |
'0' | - | - | - | C(5) |
'0' | - | - | - | C(6) |
'0' | - | - | - | C(7) |
'0' | - | - | - | C(8) |
'0' | - | - | - | C(9) |
D[24] | ||||
D[25] | ||||
'0' | - | - | - | C[0] |
'0' | - | - | - | C[1] |
D[28] | Y[6] | Y[2] | Y[2] | A[0] |
D[29] | Y[7] | Y[3] | Y[3] | A[1] |
D[30] | CbCr[6] | CbCr[2] | CbCr[2] | B[0] |
D[31] | CbCr[7] | CbCr[3] | CbCr[3] | B[1] |
V-by-One Data Map Mode 4 | ||
---|---|---|
V-by-One Input Data Bit | 18bpp YCbCr 4:2:2 (2) | Mapper Output |
D[0] | CbCr[1] | B(2) |
D[1] | CbCr[2] | B(3) |
D[2] | CbCr[3] | B(4) |
D[3] | CbCr[4] | B(5) |
D[4] | CbCr[5] | B(6) |
D[5] | CbCr[6] | B(7) |
D[6] | CbCr[7] | B(8) |
D[7] | CbCr[8] | B(9) |
D[8] | Y[1] | A(2) |
D[9] | Y[2] | A(3) |
D[10] | Y[3] | A(4) |
D[11] | Y[4] | A(5) |
D[12] | Y[5] | A(6) |
D[13] | Y[6] | A(7) |
D[14] | Y[7] | A(8) |
D[15] | Y[8] | A(9) |
'0' | - | C(2) |
'0' | - | C(3) |
'0' | - | C(4) |
'0' | - | C(5) |
'0' | - | C(6) |
'0' | - | C(7) |
'0' | - | C(8) |
'0' | - | C(9) |
D[24] | ||
D[25] | ||
'0' | - | C[0] |
'0' | - | C[1] |
'0' | - | A[0] |
D[29] | Y[0] | A[1] |
'0' | - | B[0] |
D[31] | CbCr[0] | B[1] |
V-by-One Data Map Mode 5 | ||
---|---|---|
V-by-One Input Data Bit | 16bpp YCbCr 4:2:2 (2) | Mapper Output |
D[0] | CbCr[0] | B(2) |
D[1] | CbCr[1] | B(3) |
D[2] | CbCr[2] | B(4) |
D[3] | CbCr[3] | B(5) |
D[4] | CbCr[4] | B(6) |
D[5] | CbCr[5] | B(7) |
D[6] | CbCr[6] | B(8) |
D[7] | CbCr[7] | B(9) |
D[8] | Y[0] | A(2) |
D[9] | Y[1] | A(3) |
D[10] | Y[2] | A(4) |
D[11] | Y[3] | A(5) |
D[12] | Y[4] | A(6) |
D[13] | Y[5] | A(7) |
D[14] | Y[6] | A(8) |
D[15] | Y[7] | A(9) |
'0' | - | C(2) |
'0' | - | C(3) |
'0' | - | C(4) |
'0' | - | C(5) |
'0' | - | C(6) |
'0' | - | C(7) |
'0' | - | C(8) |
'0' | - | C(9) |
D[24] | ||
D[25] | ||
'0' | - | C[0] |
'0' | - | C[1] |
'0' | - | A[0] |
'0' | - | A[1] |
'0' | - | B[0] |
'0' | - | B[1] |
V-by-One Data Map Mode 6 | |||||
---|---|---|---|---|---|
V-by-One Input Data Bit | 12bpp YCbCr 4:2:0 Even Line(2) | 12bpp YCbCr 4:2:0 Odd Line (2) | 10bpp YCbCr 4:2:0 Even Line | 10bpp YCbCr 4:2:0 Odd Line | Mapper Output |
D[0] | Y01[4] | Y01[4] | Y01[2] | Y11[2] | C(2) |
D[1] | Y01[5] | Y01[5] | Y01[3] | Y11[3] | C(3) |
D[2] | Y01[6] | Y01[6] | Y01[4] | Y11[4] | C(4) |
D[3] | Y01[7] | Y01[7] | Y01[5] | Y11[5] | C(5) |
D[4] | Y01[8] | Y01[8] | Y01[6] | Y11[6] | C(6) |
D[5] | Y01[9] | Y01[9] | Y01[7] | Y11[7] | C(7) |
D[6] | Y01[10] | Y01[10] | Y01[8] | Y11[8] | C(8) |
D[7] | Y01[11] | Y01[11] | Y01[9] | Y11[9] | C(9) |
D[8] | Y00[4] | Y00[4] | Y00[2] | Y10[2] | A(2) |
D[9] | Y00[5] | Y00[5] | Y00[3] | Y10[3] | A(3) |
D[10] | Y00[6] | Y00[6] | Y00[4] | Y10[4] | A(4) |
D[11] | Y00[7] | Y00[7] | Y00[5] | Y10[5] | A(5) |
D[12] | Y00[8] | Y00[8] | Y00[6] | Y10[6] | A(6) |
D[13] | Y00[9] | Y00[9] | Y00[7] | Y10[7] | A(7) |
D[14] | Y00[10] | Y00[10] | Y00[8] | Y10[8] | A(8) |
D[15] | Y00[11] | Y00[11] | Y00[9] | Y10[9] | A(9) |
D[16] | Cb00[4] | Cr00[4] | Cb00[2] | Cr00[2] | B(2) |
D[17] | Cb00[5] | Cr00[5] | Cb00[3] | Cr00[3] | B(3) |
D[18] | Cb00[6] | Cr00[6] | Cb00[4] | Cr00[4] | B(4) |
D[19] | Cb00[7] | Cr00[7] | Cb00[5] | Cr00[5] | B(5) |
D[20] | Cb00[8] | Cr00[8] | Cb00[6] | Cr00[6] | B(6) |
D[21] | Cb00[9] | Cr00[9] | Cb00[7] | Cr00[7] | B(7) |
D[22] | Cb00[10] | Cr00[10] | Cb00[8] | Cr00[8] | B(8) |
D[23] | Cb00[11] | Cr00[11] | Cb00[9] | Cr00[9] | B(9) |
D[24] | |||||
D[25] | |||||
D[26] | Cb00[2] | Cr00[2] | Cb00[0] | Cr00[0] | B[0] |
D[27] | Cb00[3] | Cr00[3] | Cb00[1] | Cr00[1] | B[1] |
D[28] | Y00[2] | Y10[2] | Y00[0] | Y10[0] | A[0] |
D[29] | Y00[3] | Y10[3] | Y00[1] | Y10[1] | A[1] |
D[30] | Y01[2] | Y11[2] | Y01[0] | Y11[0] | C[0] |
D[31] | Y01[3] | Y11[3] | Y01[1] | Y11[1] | C[1] |
V-by-One Data Map Mode 7 | |||
---|---|---|---|
V-by-One Input Data Bit | 8bpp YCbCr 4:2:0 Even Line (2) | 8bpp YCbCr 4:2:0 Odd Line (2) | Mapper Output |
D[0] | Y01[0] | Y11[0] | C(2) |
D[1] | Y01[1] | Y11[1] | C(3) |
D[2] | Y01[2] | Y11[2] | C(4) |
D[3] | Y01[3] | Y11[3] | C(5) |
D[4] | Y01[4] | Y11[4] | C(6) |
D[5] | Y01[5] | Y11[5] | C(7) |
D[6] | Y01[6] | Y11[6] | C(8) |
D[7] | Y01[7] | Y11[7] | C(9) |
D[8] | Y00[0] | Y10[0] | A(2) |
D[9] | Y00[1] | Y10[1] | A(3) |
D[10] | Y00[2] | Y10[2] | A(4) |
D[11] | Y00[3] | Y10[3] | A(5) |
D[12] | Y00[4] | Y10[4] | A(6) |
D[13] | Y00[5] | Y10[5] | A(7) |
D[14] | Y00[6] | Y10[6] | A(8) |
D[15] | Y00[7] | Y10[7] | A(9) |
D[16] | Cb00[0] | Cr00[0] | B(2) |
D[17] | Cb00[1] | Cr00[1] | B(3) |
D[18] | Cb00[2] | Cr00[2] | B(4) |
D[19] | Cb00[3] | Cr00[3] | B(5) |
D[20] | Cb00[4] | Cr00[4] | B(6) |
D[21] | Cb00[5] | Cr00[5] | B(7) |
D[22] | Cb00[6] | Cr00[6] | B(8) |
D[23] | Cb00[7] | Cr00[7] | B(9) |
D[24] | |||
D[25] | |||
'0' | - | - | B[0] |
'0' | - | - | B[1] |
'0' | - | - | A[0] |
'0' | - | - | A[1] |
'0' | - | - | C[0] |
'0' | - | - | C[1] |
V-by-One Data Map Mode 8 | |||
---|---|---|---|
V-by-One Input Data Bit | 10bpp YCbCr 4:2:0 Even Line | 10bpp YCbCr 4:2:0 Odd Line | Mapper Output |
D[0] | Y00[2] | Y10[2] | A(2) |
D[1] | Y003] | Y10[3] | A(3) |
D[2] | Y00[4] | Y10[4] | A(4) |
D[3] | Y00[5] | Y10[5] | A(5) |
D[4] | Y00[6] | Y10[6] | A(6) |
D[5] | Y00[7] | Y10[7] | A(7) |
D[6] | Y00[8] | Y10[8] | A(8) |
D[7] | Y00[9] | Y10[9] | A(9) |
D[8] | Cb00[2] | Cr00[2] | B(2) |
D[9] | Cb00[3] | Cr00[3] | B(3) |
D[10] | Cb00[4] | Cr00[4] | B(4) |
D[11] | Cb00[5] | Cr00[5] | B(5) |
D[12] | Cb00[6] | Cr00[6] | B(6) |
D[13] | Cb00[7] | Cr00[7] | B(7) |
D[14] | Cb00[8] | Cr00[8] | B(8) |
D[15] | Cb00[9] | Cr00[9] | B(9) |
D[16] | Y01[2] | Y11[2] | C(2) |
D[17] | Y01[3] | Y11[3] | C(3) |
D[18] | Y01[4] | Y11[4] | C(4) |
D[19] | Y01[5] | Y11[5] | C(5) |
D[20] | Y01[6] | Y11[6] | C(6) |
D[21] | Y01[7] | Y11[7] | C(7) |
D[22] | Y01[8] | Y11[8] | C(8) |
D[23] | Y01[9] | Y11[9] | C(9) |
D[24] | |||
D[25] | |||
D[26] | Y01[0] | Y11[0] | C[0] |
D[27] | Y01[1] | Y11[1] | C[1] |
D[28] | Cb00[0] | Cr00[0] | B[0] |
D[29] | Cb00[1] | Cr00[1] | B[1] |
D[30] | Y00[0] | Y10[0] | A[0] |
D[31] | Y00[1] | Y10[1] | A[1] |
V-by-One Data Map Mode 9 | |||
---|---|---|---|
V-by-One Input Data Bit | 8bpp YCbCr 4:2:0 Even Line (2) | 8bpp YCbCr 4:2:0 Odd Line (2) | Mapper Output |
D[0] | Y00[0] | Y10[0] | A(2) |
D[1] | Y00[1] | Y10[1] | A(3) |
D[2] | Y00[2] | Y10[2] | A(4) |
D[3] | Y003] | Y10[3] | A(5) |
D[4] | Y00[4] | Y10[4] | A(6) |
D[5] | Y00[5] | Y10[5] | A(7) |
D[6] | Y00[6] | Y10[6] | A(8) |
D[7] | Y00[7] | Y10[7] | A(9) |
D[8] | Cb00[0] | Cr00[0] | B(2) |
D[9] | Cb00[1] | Cr00[1] | B(3) |
D[10] | Cb00[2] | Cr00[2] | B(4) |
D[11] | Cb00[3] | Cr00[3] | B(5) |
D[12] | Cb00[4] | Cr00[4] | B(6) |
D[13] | Cb00[5] | Cr00[5] | B(7) |
D[14] | Cb00[6] | Cr00[6] | B(8) |
D[15] | Cb00[7] | Cr00[7] | B(9) |
D[16] | Y01[0] | Y11[0] | C(2) |
D[17] | Y01[1] | Y11[1] | C(3) |
D[18] | Y01[2] | Y11[2] | C(4) |
D[19] | Y01[3] | Y11[3] | C(5) |
D[20] | Y01[4] | Y11[4] | C(6) |
D[21] | Y01[5] | Y11[5] | C(7) |
D[22] | Y01[6] | Y11[6] | C(8) |
D[23] | Y01[7] | Y11[7] | C(9) |
D[24] | |||
D[25] | |||
'0' | - | - | C[0] |
'0' | - | - | C[1] |
'0' | - | - | B[0] |
'0' | - | - | B[1] |
'0' | - | - | A[0] |
'0' | - | - | A[1] |