7.3.7 Loss of Input Power Event
A few key PDN design items needed to enable a controlled and compliant SoC power down sequence for a “Loss of Input Power” event are:
- “Loss of Input Power” early warning
- TI EVM and Reference Design Study SCHs and PDNs achieve this by using the 1st Stage Converter’s (i.e. LM536033-Q1) Power Good status output to enable and disable the 2nd Stage PMIC devices (i.e. TPS65917/919, LP8733, and LP8732). If a different 1st Stage Converter is used, care must be taken to ensure an adequate “PG_Status” or “Vbatt_Status” signal is provided that can disable 2nd Stage PMIC to begin a controlled and compliant SoC power down sequence. The total elapsed time from asserting “PG_Status” low until SoC’s PMIC input voltage reaches minimum level of 2.75V should be minimum of 1.5 ms and 2 ms preferred.
- Maximize discharge time of 1st Stage Vout (VSYS_3V3 power rail = input voltage to SoC PMIC).
- TI EVM and Reference Design Study SCHs and PDNs achieve this by opening an in-line load switch immediately upon “PG_Status” low assertion in order to remove the SoC’s 3.3V IO load current from VSYS_3V3. This will extend the VSYS_3V3 power rail’s discharge time in order to maximize elapsed time for allowing SoC PMIC to execute a controlled and compliant power down sequence. Care should be taken to either disable or isolate any additional peripheral components that may be loading the VSYS_3V3 rail as well.
- Sufficient bulk decoupling capacitance on the 1st Stage Vout (VSYS_3V3 per PDN) that allows for desired 1.5 – 2 ms elapsed time as described above.
- TI EVM and Reference Design Study SCHs and PDNs achieve this by using 200µF of total capacitance on VSYS_3V3. The 1st Stage Converter (i.e. LM536033-Q1) can typically drive a max of 400 µF to help extend VSYS_3V3 discharge time for a compliant SoC power down sequence.
- Optimizing the 2nd Stage SoC PMIC’s OTP settings that determines SoC power up and down sequences and total elapsed time needed for a controlled sequence.
- TI EVM and Reference Design Study SCHs and PDNs achieve this by using optimized OTPs per the SCH and components used. The definition of these OTPs is captured in the detailed timing diagrams for both power up and down sequences. The PDN diagram typically shows a recommended PMIC OTP ID based upon the SoC and DDR memory types.