SPRS975H August   2016  – February 2020 DRA780 , DRA781 , DRA782 , DRA783 , DRA784 , DRA785 , DRA786 , DRA787 , DRA788

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  SD_DAC
      4. 4.3.4  ADC
      5. 4.3.5  Camera Control
      6. 4.3.6  CPI
      7. 4.3.7  CSI2
      8. 4.3.8  EMIF
      9. 4.3.9  GPMC
      10. 4.3.10 Timers
      11. 4.3.11 I2C
      12. 4.3.12 UART
      13. 4.3.13 McSPI
      14. 4.3.14 QSPI
      15. 4.3.15 McASP
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 SDIO Controller
      19. 4.3.19 GPIO
      20. 4.3.20 PWMSS
      21. 4.3.21 ATL
      22. 4.3.22 Test Interfaces
      23. 4.3.23 System and Miscellaneous
        1. 4.3.23.1 Sysboot
        2. 4.3.23.2 Power, Reset and Clock Management (PRCM)
        3. 4.3.23.3 Enhanced Direct Memory Access (EDMA)
        4. 4.3.23.4 Interrupt Controllers (INTC)
      24. 4.3.24 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS Analog OSC Buffers DC Electrical Characteristics
      6. Table 5-11 Dual Voltage LVCMOS DC Electrical Characteristics
      7. Table 5-12 Analog-to-Digital ADC Subsystem Electrical Specifications
    8. 5.8 Thermal Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Timing Requirements and Switching Characteristics
      1. 5.9.1 Timing Parameters and Information
        1. 5.9.1.1 Parameter Information
          1. 5.9.1.1.1 1.8 V and 3.3 V Signal Transition Levels
          2. 5.9.1.1.2 1.8 V and 3.3 V Signal Transition Rates
          3. 5.9.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.9.2 Interface Clock Specifications
        1. 5.9.2.1 Interface Clock Terminology
        2. 5.9.2.2 Interface Clock Frequency
      3. 5.9.3 Power Supply Sequences
      4. 5.9.4 Clock Specifications
        1. 5.9.4.1 Input Clocks / Oscillators
          1. 5.9.4.1.1 OSC0 External Crystal
          2. 5.9.4.1.2 OSC0 Input Clock
          3. 5.9.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.9.4.1.3.1 OSC1 External Crystal
            2. 5.9.4.1.3.2 OSC1 Input Clock
          4. 5.9.4.1.4 RC On-die Oscillator Clock
        2. 5.9.4.2 Output Clocks
        3. 5.9.4.3 DPLLs, DLLs
          1. 5.9.4.3.1 DPLL Characteristics
          2. 5.9.4.3.2 DLL Characteristics
            1. 5.9.4.3.2.1 DPLL and DLL Noise Isolation
      5. 5.9.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.9.6 Peripherals
        1. 5.9.6.1  Timing Test Conditions
        2. 5.9.6.2  VIP
        3. 5.9.6.3  DSS
        4. 5.9.6.4  EMIF
        5. 5.9.6.5  GPMC
          1. 5.9.6.5.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.9.6.5.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.9.6.5.3 GPMC/NAND Flash Interface Asynchronous Timing
        6. 5.9.6.6  GP Timers
          1. 5.9.6.6.1 GP Timer Features
        7. 5.9.6.7  I2C
          1. Table 5-39 Timing Requirements for I2C Input Timings
          2. Table 5-40 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        8. 5.9.6.8  UART
          1. Table 5-41 Timing Requirements for UART
          2. Table 5-42 Switching Characteristics Over Recommended Operating Conditions for UART
        9. 5.9.6.9  McSPI
        10. 5.9.6.10 QSPI
        11. 5.9.6.11 McASP
          1. Table 5-50 Timing Requirements for McASP1
          2. Table 5-51 Timing Requirements for McASP2
          3. Table 5-52 Timing Requirements for McASP3
          4. Table 5-53 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-54 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-55 Switching Characteristics Over Recommended Operating Conditions for McASP3
        12. 5.9.6.12 DCAN and MCAN
          1. 5.9.6.12.1 DCAN
          2. 5.9.6.12.2 MCAN
          3. Table 5-58 Timing Requirements for CAN Receive
          4. Table 5-59 Switching Characteristics Over Recommended Operating Conditions for CAN Transmit
        13. 5.9.6.13 GMAC_SW
          1. 5.9.6.13.1 GMAC MDIO Interface Timings
          2. 5.9.6.13.2 GMAC RGMII Timings
            1. Table 5-63 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-64 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-65 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-66 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        14. 5.9.6.14 SDIO Controller
          1. 5.9.6.14.1 MMC, SD Default Speed
          2. 5.9.6.14.2 MMC, SD High Speed
          3. 5.9.6.14.3 MMC, SD and SDIO SDR12 Mode
          4. 5.9.6.14.4 MMC, SD SDR25 Mode
        15. 5.9.6.15 GPIO
        16. 5.9.6.16 ATL
          1. 5.9.6.16.1 ATL Electrical Data/Timing
            1. Table 5-77 Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
      7. 5.9.7 Emulation and Debug Subsystem
        1. 5.9.7.1 JTAG Electrical Data/Timing
          1. Table 5-78 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 5-79 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 5-80 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 5-81 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.9.7.2 Trace Port Interface Unit (TPIU)
          1. 5.9.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Processor Subsystems
      1. 6.2.1 DSP Subsystem
      2. 6.2.2 IPU
    3. 6.3 Accelerators and Coprocessors
      1. 6.3.1 EVE
    4. 6.4 Other Subsystems
      1. 6.4.1 Memory Subsystem
        1. 6.4.1.1 EMIF
        2. 6.4.1.2 GPMC
        3. 6.4.1.3 ELM
        4. 6.4.1.4 OCMC
      2. 6.4.2 Interprocessor Communication
        1. 6.4.2.1 Mailbox
        2. 6.4.2.2 Spinlock
      3. 6.4.3 Interrupt Controller
      4. 6.4.4 EDMA
      5. 6.4.5 Peripherals
        1. 6.4.5.1  VIP
        2. 6.4.5.2  DSS
        3. 6.4.5.3  ATL
        4. 6.4.5.4  ADC
        5. 6.4.5.5  Timers
          1. 6.4.5.5.1 General-Purpose Timers
          2. 6.4.5.5.2 32-kHz Synchronized Timer (COUNTER_32K)
        6. 6.4.5.6  I2C
        7. 6.4.5.7  UART
        8. 6.4.5.8  McSPI
        9. 6.4.5.9  QSPI
        10. 6.4.5.10 McASP
        11. 6.4.5.11 DCAN
        12. 6.4.5.12 MCAN
        13. 6.4.5.13 GMAC_SW
        14. 6.4.5.14 SDIO
        15. 6.4.5.15 GPIO
        16. 6.4.5.16 ePWM
        17. 6.4.5.17 eCAP
        18. 6.4.5.18 eQEP
      6. 6.4.6 On-Chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing-Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing-Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd_dspeve Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
        1. 7.4.2.1 If QSPI is operated in Mode 0 (POL=0, PHA=0):
        2. 7.4.2.2 If QSPI is operated in Mode 3 (POL=1, PHA=1):
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7 DDR2 Board Design and Layout Guidelines
      1. 7.7.1 DDR2 General Board Layout Guidelines
      2. 7.7.2 DDR2 Board Design and Layout Guidelines
        1. 7.7.2.1 Board Designs
        2. 7.7.2.2 DDR2 Interface
          1. 7.7.2.2.1  DDR2 Interface Schematic
          2. 7.7.2.2.2  Compatible JEDEC DDR2 Devices
          3. 7.7.2.2.3  PCB Stackup
          4. 7.7.2.2.4  Placement
          5. 7.7.2.2.5  DDR2 Keepout Region
          6. 7.7.2.2.6  Bulk Bypass Capacitors
          7. 7.7.2.2.7  High Speed Bypass Capacitors
          8. 7.7.2.2.8  Net Classes
          9. 7.7.2.2.9  DDR2 Signal Termination
          10. 7.7.2.2.10 VREF Routing
        3. 7.7.2.3 DDR2 CK and ADDR_CTRL Routing
    8. 7.8 DDR3 Board Design and Layout Guidelines
      1. 7.8.1 DDR3 General Board Layout Guidelines
      2. 7.8.2 DDR3 Board Design and Layout Guidelines
        1. 7.8.2.1  Board Designs
        2. 7.8.2.2  DDR3 Device Combinations
        3. 7.8.2.3  DDR3 Interface Schematic
          1. 7.8.2.3.1 32-Bit DDR3 Interface
          2. 7.8.2.3.2 16-Bit DDR3 Interface
        4. 7.8.2.4  Compatible JEDEC DDR3 Devices
        5. 7.8.2.5  PCB Stackup
        6. 7.8.2.6  Placement
        7. 7.8.2.7  DDR3 Keepout Region
        8. 7.8.2.8  Bulk Bypass Capacitors
        9. 7.8.2.9  High Speed Bypass Capacitors
          1. 7.8.2.9.1 Return Current Bypass Capacitors
        10. 7.8.2.10 Net Classes
        11. 7.8.2.11 DDR3 Signal Termination
        12. 7.8.2.12 VTT
        13. 7.8.2.13 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.8.2.13.1 Three DDR3 Devices
            1. 7.8.2.13.1.1 CK and ADDR_CTRL Topologies, Three DDR3 Devices
            2. 7.8.2.13.1.2 CK and ADDR_CTRL Routing, Three DDR3 Devices
          2. 7.8.2.13.2 Two DDR3 Devices
            1. 7.8.2.13.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.8.2.13.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.8.2.13.3 One DDR3 Device
            1. 7.8.2.13.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.8.2.13.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        14. 7.8.2.14 Data Topologies and Routing Definition
          1. 7.8.2.14.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.8.2.14.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        15. 7.8.2.15 Routing Specification
          1. 7.8.2.15.1 CK and ADDR_CTRL Routing Specification
          2. 7.8.2.15.2 DQS and DQ Routing Specification
    9. 7.9 CVIDEO/SD-DAC Guidelines and Electrical Data/Timing
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABF|367
Thermal pad, mechanical data (Package|Pins)
Orderable Information

On-Chip Debug

Debugging a system that contains an embedded processor involves an environment that connects high-level debugging software running on a host computer to a low-level debug interface supported by the target device. Between these levels, a debug and trace controller (DTC) facilitates communication between the host debugger and the debug support logic on the target chip.

The DTC is a combination of hardware and software that connects the host debugger to the target system. The DTC uses one or more hardware interfaces and/or protocols to convert actions dictated by the debugger user to JTAG commands and scans that execute the core hardware.

The debug software and hardware components let the user control multiple central processing unit (CPU) cores embedded in the device in a global or local manner. This environment provides:

  • Synchronized global starting and stopping of multiple processors
  • Starting and stopping of an individual processor
  • Each processor can generate triggers that can be used to alter the execution flow of other processors

System topics include but are not limited to:

  • System clocking and power-down issues
  • Interconnection of multiple devices
  • Trigger channels

The device deploys Texas Instrument's CTools debug technology for on-chip debug and trace support. It provides the following features:

  • External debug interfaces:
    • Primary debug interface - IEEE1149.1 (JTAG) or IEEE1149.7 (complementary superset of JTAG)
      • Used for debugger connection
      • Default mode is IEEE1149.1 but debugger can switch to IEEE1149.7 via an IEEE1149.7 adapter module
      • Controls ICEPick (generic test access port [TAP] for dynamic TAP insertion) to allow the debugger to access several debug resources through its secondary (output) JTAG ports (for more information, see section ICEPick Secondary TAPs in chapter On-Chip Debug Support of the Device TRM).
    • Debug (trace) port
      • Can be used to export processor or system trace off-chip (to an external trace receiver)
      • Can be used for cross-triggering with an external device
      • Configured through debug resources manager (DRM) module instantiated in the debug subsystem
      • For more information about debug (trace) port, see sections Debug (Trace) Port and Concurrent Debug Modes in chapter On-Chip Debug Support of the Device TRM.
  • JTAG based processor debug on:
    • C66x in DSP1, DSP2
    • Cortex-M4 (x2) in IPU
  • Dynamic TAP insertion
    • Controlled by ICEPick
    • For more information, see section Dynamic TAP Insertion in chapter On-Chip Debug Support of the Device TRM
  • Power and clock management
    • Debugger can get the status of the power domain associated to each TAP.
    • Debugger may prevent the application software switching off the power domain.
    • Application power management behavior can be preserved during debug across power transitions.
    • For more information, see section Power and Clock Management in chapter On-Chip Debug Support of the Device TRM.
  • Reset management
    • Debugger can configure ICEPick to assert, block, or extend the reset of a given subsystem.
    • For more information, see section Reset Management in chapter On-Chip Debug Support of the Device TRM.
  • Cross-triggering
    • Provides a way to propagate debug (trigger) events from one processor, subsystem, or module to another:
      • Subsystem A can be programmed to generate a debug event, which can then be exported as a global trigger across the device.
      • Subsystem B can be programmed to be sensitive to the trigger line input and to generate an action on trigger detection.
    • Two global trigger lines are implemented
    • Device-level cross-triggering is handled by the XTRIG (TI cross-trigger) module implemented in the debug subsystem
    • For more information about cross-triggering, see section Cross-Triggering in chapter On-Chip Debug Support of the Device TRM.
  • Suspend
    • Provides a way to stop a closely coupled hardware process running on a peripheral module when the host processor enters debug state
    • For more information about suspend, see section Suspend in chapter On-Chip Debug Support of the Device TRM.
  • Processor trace
    • C66x (DSP) processor trace is supported
    • Two exclusive trace sinks:
      • CoreSight Trace Port Interface Unit (CS_TPIU) – trace export to an external trace receiver
    • For more information, see section Processor Trace in chapter On-Chip Debug Support of the Device TRM.
  • System instrumentation (trace)
    • Supported by a CTools System Trace Module (CT_STM), implementing MIPI System Trace Protocol (STP) (rev 2.0)
    • Real-time software trace
      • System-on-chip (SoC) software instrumentation through CT_STM (STP2.0)
    • OCP watchpoint (OCP_WP_NOC)
      • OCP target traffic monitoring: OCP_WP_NOC can be configured to generate a trigger upon watchpoint match (that is, when target transaction attributes match the user-defined attributes).
      • SoC events trace
      • DMA transfer profiling
    • Statistics collector (performance probes)
      • Computes traffic statistics within a user-defined window and periodically reports to the user through the CT_STM interface
      • Embedded in the L3_MAIN interconnect
      • 10 instances:
        • 1 instance dedicated to target (SDRAM) load monitoring
        • 9 instances dedicated to master latency monitoring
    • Power-management events profiling (PM instrumentation [PMI])
      • Monitoring major power-management events. The PM state changes are handled as generic events and encapsulated in STP messages.
    • Clock-management events profiling CM instrumentation [CMI]) for CM_CORE_AON clocks
      • Monitoring major clock management events. The CM state changes are handled as generic events and encapsulated in STP messages.
      • One instances
        • CM1 Instrumentation (CMI1) module mapped in the PD_CORE_AON power domain
    • For more information, see section System Instrumentation in chapter On-Chip Debug Support of the Device TRM.
  • Performance monitoring
    • Supported by subsystem counter timer module (SCTM) for IPU

For more information, see chapter On-Chip Debug Support of the device TRM.