SLVSGH7B november   2022  – july 2023 DRV8410

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Diagrams
  9. 8 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 External Components
    4. 9.4 Feature Description
      1. 9.4.1 Bridge Control
        1. 9.4.1.1 Parallel Bridge Interface
      2. 9.4.2 Current Regulation
      3. 9.4.3 Protection Circuits
        1. 9.4.3.1 Overcurrent Protection (OCP)
        2. 9.4.3.2 Thermal Shutdown (TSD)
        3. 9.4.3.3 Undervoltage Lockout (UVLO)
    5. 9.5 Device Functional Modes
      1. 9.5.1 Active Mode
      2. 9.5.2 Low-Power Sleep Mode
      3. 9.5.3 Fault Mode
    6. 9.6 Pin Diagrams
      1. 9.6.1 Logic-Level Inputs
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Typical Application
        1. 10.1.1.1 Stepper Motor Application
          1. 10.1.1.1.1 Design Requirements
          2. 10.1.1.1.2 Detailed Design Procedure
            1. 10.1.1.1.2.1 Stepper Motor Speed
            2. 10.1.1.1.2.2 Current Regulation
            3. 10.1.1.1.2.3 Stepping Modes
              1. 10.1.1.1.2.3.1 Full-Stepping Operation
              2. 10.1.1.1.2.3.2 Half-Stepping Operation with Fast Decay
              3. 10.1.1.1.2.3.3 Half-Stepping Operation with Slow Decay
          3. 10.1.1.1.3 Application Curves
        2. 10.1.1.2 Dual BDC Motor Application
          1. 10.1.1.2.1 Design Requirements
          2. 10.1.1.2.2 Detailed Design Procedure
            1. 10.1.1.2.2.1 Motor Voltage
            2. 10.1.1.2.2.2 Current Regulation
            3. 10.1.1.2.2.3 Sense Resistor
          3. 10.1.1.2.3 Application Curves
        3. 10.1.1.3 Thermal Considerations
          1. 10.1.1.3.1 Maximum Output Current
          2. 10.1.1.3.2 Power Dissipation
          3. 10.1.1.3.3 Thermal Performance
            1. 10.1.1.3.3.1 Steady-State Thermal Performance
            2. 10.1.1.3.3.2 Transient Thermal Performance
        4. 10.1.1.4 Multi-Sourcing with Standard Motor Driver Pinout
  12. 11Power Supply Recommendations
    1. 11.1 Bulk Capacitance
    2. 11.2 Power Supply and Logic Sequencing
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|16
  • RTE|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.4.1.1 Parallel Bridge Interface

In the parallel bridge interface, the DRV8410 is configured to drive a higher current brushed-DC (BDC) motor by connecting the driver outputs in parallel to reduce the RDS(ON) by a factor of two. Figure 9-3 shows an example of how to connect the pins on the device. To use parallel bridge interface operation, connect AIN1 and BIN1 to the same control signal, IN1, and connect AIN2 and BIN2 to the same control signal, IN2. Similarly, connect AOUT1 and BOUT1 to the same output node, OUT1, and connect AOUT2 and BOUT2 to the same output node, OUT2. AISEN and BISEN must be connected to the same ground plane.

Current regulation may be used if AISEN and BISEN are connected to the same sense resistor. The voltage of the xISEN pins will be compared to the internal VTRIP reference (0.2 V) to set the current regulation level.

GUID-20210818-SS0I-FPCT-D6WX-DZTWSJZHKXMT-low.svgFigure 9-3 Parallel Mode Connections

This mode can deliver the full functionality of the BDC motor control with all four modes (forward, reverse, coast, and brake mode). Table 9-4 shows the control interface states in parallel mode.

Table 9-4 Parallel H-Bridge Control
nSLEEPIN1 (AIN1 & BIN1)IN2 (AIN2 & BIN2)OUT1 (AOUT1 & BOUT1OUT2 (AOUT2 & BOUT2)DESCRIPTION
0XXHigh-ZHigh-ZLow-power sleep mode
100High-ZHigh-ZCoast; H-bridge disabled to High-Z
101LHReverse (Current OUT2 → OUT1)
110HLForward (Current OUT1 → OUT2)
111LLBrake; low-side slow decay