SLVSEE9D April 2020 – April 2021 DRV8889-Q1
PRODUCTION DATA
Table 7-16 lists the memory-mapped registers for the DRV8889-Q1 device. All register addresses not listed in Table 7-16 should be considered as reserved locations and the register contents should not be modified.
Table 7-16 lists the memory-mapped registers for the DRV8889A-Q1 device. All register addresses not listed in Table 7-16 should be considered as reserved locations and the register contents should not be modified.
Register Name |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Access Type |
Address |
---|---|---|---|---|---|---|---|---|---|---|
FAULT Status | FAULT | SPI_ERROR | UVLO | CPUV | OCP | STL | TF | OL | R | 0x00 |
DIAG Status 1 | OCP_LS2_B | OCP_HS2_B | OCP_LS1_B | OCP_HS1_B | OCP_LS2_A | OCP_HS2_A | OCP_LS1_A | OCP_HS1_A | R | 0x01 |
DIAG Status 2 | UTW | OTW | OTS | STL_LRN_OK | STALL | RSVD | OL_B | OL_A | R | 0x02 |
CTRL1 | TRQ_DAC [3:0] | RSVD | SLEW_RATE [1:0] | RW | 0x03 | |||||
CTRL2 | DIS_OUT | RSVD | TOFF [1:0] | DECAY [2:0] | RW | 0x04 | ||||
CTRL3 | DIR | STEP | SPI_DIR | SPI_STEP | MICROSTEP_MODE [3:0] | RW | 0x05 | |||
CTRL4 | CLR_FLT | LOCK [2:0] | EN_OL | OCP_MODE | OTSD_MODE | TW_REP | RW | 0x06 | ||
CTRL5 | RSVD | STL_LRN | EN_STL | STL_REP | RSVD | RW | 0x07 | |||
CTRL6 | STALL_TH [7:0] | RW | 0x08 | |||||||
CTRL7 | TRQ_COUNT [7:0] | R | 0x09 | |||||||
CTRL8 | RSVD | REV_ID [3:0] | R | 0x0A |
Register Name |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Access Type |
Address |
---|---|---|---|---|---|---|---|---|---|---|
FAULT Status | FAULT | SPI_ERROR | UVLO | CPUV | OCP | STL | TF | OL | R | 0x00 |
DIAG Status 1 | OCP_LS2_B | OCP_HS2_B | OCP_LS1_B | OCP_HS1_B | OCP_LS2_A | OCP_HS2_A | OCP_LS1_A | OCP_HS1_A | R | 0x01 |
DIAG Status 2 | UTW | OTW | OTS | STL_LRN_OK | STALL | RSVD | OL_B | OL_A | R | 0x02 |
CTRL1 | TRQ_DAC [3:0] | RSVD | SLEW_RATE [1:0] | RW | 0x03 | |||||
CTRL2 | DIS_OUT | RSVD | TOFF [1:0] | DECAY [2:0] | RW | 0x04 | ||||
CTRL3 | DIR | STEP | SPI_DIR | SPI_STEP | MICROSTEP_MODE [3:0] | RW | 0x05 | |||
CTRL4 | CLR_FLT | LOCK [2:0] | EN_OL | OCP_MODE | OTSD_MODE | TW_REP | RW | 0x06 | ||
CTRL5 | RSVD | STL_LRN | EN_STL | STL_REP | OL_TIME [1:0] | EN_SR_BLANK | RW | 0x07 | ||
CTRL6 | STALL_TH [7:0] | RW | 0x08 | |||||||
CTRL7 | TRQ_COUNT [7:0] | R | 0x09 | |||||||
CTRL8 | RSVD | REV_ID [3:0] | R | 0x0A |
The differences between the register maps of the DRV8889-Q1 and DRV8889A-Q1 are - DRV8889A-Q1 has OL_TIME [1:0] and EN_SR_BLANK bits in CTRL5 register to program open-load detection time and slow-decay to drive mode blanking time. Also, the default value of the DIS_OUT bit in CTRL2 register is different in DRV8889A-Q1.
Complex bit access types are encoded to fit into small table cells. Table 7-18 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
The status registers are used to reporting warning and fault conditions. Status registers are read-only registers
Table 7-19 lists the memory-mapped registers for the status registers. All register offset addresses not listed in Table 7-19 should be considered as reserved locations and the register contents should not be modified.
FAULT status is shown in Figure 7-33 and described in Figure 7-33.
Read-only
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FAULT | SPI_ERROR | UVLO | CPUV | OCP | STL | TF | OL |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | FAULT | R | 0b | When nFAULT pin is at 1, FAULT bit is 0. When nFAULT pin is at 0, FAULT bit is 1. |
6 | SPI_ERROR | R | 0b | Indicates SPI protocol errors, such as more SCLK pulses than are required or SCLK is absent even though nSCS is low. Becomes high in fault and the nFAULT pin is driven low. Normal operation resumes when the protocol error is removed and a clear faults command has been issued either through the CLR_FLT bit or an nSLEEP reset pulse. |
5 | UVLO | R | 0b | Indicates an undervoltage lockout fault condition. |
4 | CPUV | R | 0b | Indicates charge pump undervoltage fault condition. |
3 | OCP | R | 0b | Indicates overcurrent fault condition |
2 | STL | R | 0b | Indicates motor stall condition. |
1 | TF | R | 0b | Logic OR of the overtemperature warning, undertemperature warning and overtemperature shutdown. |
0 | OL | R | 0b | Indicates open-load condition. |
DIAG Status 1 is shown in Figure 7-34 and described in Table 7-21.
Read-only
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCP_LS2_B | OCP_HS2_B | OCP_LS1_B | OCP_HS1_B | OCP_LS2_A | OCP_HS2_A | OCP_LS1_A | OCP_HS1_A |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | OCP_LS2_B | R | 0b | Indicates overcurrent fault on the low-side FET of half bridge 2 in BOUT |
6 | OCP_HS2_B | R | 0b | Indicates overcurrent fault on the high-side FET of half bridge 2 in BOUT |
5 | OCP_LS1_B | R | 0b | Indicates overcurrent fault on the low-side FET of half bridge 1 in BOUT |
4 | OCP_HS1_B | R | 0b | Indicates overcurrent fault on the high-side FET of half bridge 1 in BOUT |
3 | OCP_LS2_A | R | 0b | Indicates overcurrent fault on the low-side FET of half bridge 2 in AOUT |
2 | OCP_HS2_A | R | 0b | Indicates overcurrent fault on the high-side FET of half bridge 2 in AOUT |
1 | OCP_LS1_A | R | 0b | Indicates overcurrent fault on the low-side FET of half bridge 1 in AOUT |
0 | OCP_HS1_A | R | 0b | Indicates overcurrent fault on the high-side FET of half bridge 1 in AOUT |
DIAG Status 2 is shown in Figure 7-35 and described in Table 7-22.
Read-only
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UTW | OTW | OTS | STL_LRN_OK | STALL | RSVD | OL_B | OL_A |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | UTW | R | 0b | Indicates undertemperature warning. |
6 | OTW | R | 0b | Indicates overtemperature warning. |
5 | OTS | R | 0b | Indicates overtemperature shutdown. |
4 | STL_LRN_OK | R | 0b | Indicates stall detection learning is successful |
3 | STALL | R | 0b | Indicates motor stall condition |
2 | RSVD | R | 0b | Reserved. |
1 | OL_B | R | 0b | Indicates open-load detection on BOUT |
0 | OL_A | R | 0b | Indicates open-load detection on AOUT |
The IC control registers are used to configure the device. Status registers are read and write capable.
Table 7-23 lists the memory-mapped registers for the control registers. All register offset addresses not listed in Table 7-23 should be considered as reserved locations and the register contents should not be modified.
CTRL1 control is shown in Figure 7-36 and described in Table 7-24.
Read/Write
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRQ_DAC [3:0] | RSVD | SLEW_RATE [1:0] | |||||
R/W-0000b | R/W-00b | R/W-00b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7-4 | TRQ_DAC [3:0] | R/W | 0000b | 0000b = 100% 0001b = 93.75% 0010b = 87.5% 0011b = 81.25% 0100b = 75% 0101b = 68.75% 0110b = 62.5% 0111b = 56.25% 1000b = 50% 1001b = 43.75% 1010b = 37.5% 1011b = 31.25% 1100b = 25% 1101b = 18.75% 1110b = 12.5% 1111b = 6.25% |
3-2 | RSVD | R/W | 00b | Reserved |
1-0 | SLEW_RATE [1:0] | R/W | 00b | 00b = 10-V/µs 01b = 35-V/µs 10b = 50-V/µs 11b = 105-V/µs |
CTRL2 is shown in Figure 7-37 and CTRL2 Control Register for DRV8889A-Q1 and described in Table 7-25.
Read/Write
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIS_OUT | RSVD | TOFF [1:0] | DECAY [2:0] | ||||
R/W-0b | R/W-00b | R/W-01b | R/W-111b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | DIS_OUT | R/W | 0b (DRV8889-Q1) 1b (DRV8889A-Q1) | Write '1' to Hi-Z all outputs. Write '0' to enable all outputs. OR'ed with DRVOFF pin. To prevent false OL detection, ensure OL fault detection is disabled by writing '0' to EN_OL bit, before making the outputs Hi-Z by writing '1' to DIS_OUT. |
6-5 | RSVD | R/W | 00b | Reserved |
4-3 | TOFF [1:0] | R/W | 01b | 00b = 7 µs 01b = 16 µs 10b = 24 µs 11b = 32 µs |
2-0 | DECAY [2:0] | R/W | 111b | 000b = Increasing SLOW, decreasing SLOW 001b = Increasing SLOW, decreasing MIXED 30% 010b = Increasing SLOW, decreasing MIXED 60% 011b = Increasing SLOW, decreasing FAST 100b = Increasing MIXED 30%, decreasing MIXED 30% 101b = Increasing MIXED 60%, decreasing MIXED 60% 110b = Smart tune Dynamic Decay 111b = Smart tune Ripple Control |
CTRL3 is shown in Figure 7-38 and described in Table 7-26.
Read/Write
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIR | STEP | SPI_DIR | SPI_STEP | MICROSTEP_MODE [3:0] | |||
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0000b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | DIR | R/W | 0b | Direction input. Logic '1' sets the direction of stepping, when SPI_DIR = 1. |
6 | STEP | R/W | 0b | Step input. Logic '1' causes the indexer to advance one step, when SPI_STEP = 1. This bit is self-clearing, automatically becomes '0' after writing '1'. |
5 | SPI_DIR | R/W | 0b | 0b = Outputs follow input pin for DIR 1b = Outputs follow SPI registers DIR |
4 | SPI_STEP | R/W | 0b | 0b = Outputs follow input pin for STEP 1b = Outputs follow SPI registers STEP |
3-0 | MICROSTEP_MODE [3:0] | R/W | 0000b | 0000b = Full step (2-phase excitation) with 100% current 0001b = Full step (2-phase excitation) with 71% current 0010b = Non-circular 1/2 step 0011b = 1/2 step 0100b = 1/4 step 0101b = 1/8 step 0110b = 1/16 step 0111b = 1/32 step 1000b = 1/64 step 1001b = 1/128 step 1010b = 1/256 step 1011b to 1111b = Reserved |
CTRL4 is shown in Figure 7-39 and described in Table 7-27.
Read/Write
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR_FLT | LOCK [2:0] | EN_OL | OCP_MODE | OTSD_MODE | TW_REP | ||
R/W-0b | R/W-011b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | CLR_FLT | R/W | 0b | Write '1' to this bit to clear all latched fault bits. This bit automatically resets after being written. |
6-4 | LOCK [2:0] | R/W | 011b | Write 110b to lock the settings by ignoring further register writes except to these bits and address 0x06h bit 7 (CLR_FLT). Writing any sequence other than 110b has no effect when unlocked. Write 011b to this register to unlock all registers. Writing any sequence other than 011b has no effect when locked. |
3 | EN_OL | R/W | 0b | Write '1' to enable open load detection |
2 | OCP_MODE | R/W | 0b | 0b = Overcurrent condition causes a latched fault 1b = Overcurrent condition causes an automatic retrying fault |
1 | OTSD_MODE | R/W | 0b | 0b = Overtemperature condition will cause latched fault 1b = Overtemperature condition will cause automatic recovery fault |
0 | TW_REP | R/W | 0b | 0b = Overtemperature or undertemperature warning is not reported on the nFAULT line 1b = Overtemperature or undertemperature warning is reported on the nFAULT line |
CTRL5 for DRV8889A-Q1 is shown in Figure 7-40 and described in Table 7-28.
CTRL5 for DRV8889-Q1 is shown in Figure 7-41 and described in Table 7-29.
DRV8889A-Q1 features programable open-load detection time using the OL_TIME [1:0] bits and programmable slow-decay to drive blanking time using the EN_SR_BLANK bit.
Read/Write
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | STL_LRN | EN_STL | STL_REP | OL_TIME [1:0] | EN_SR_BLANK | ||
R/W-00b | R/W-0b | R/W-0b | R/W-1b | R/W-00b | R/W-0b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | STL_LRN | EN_STL | STL_REP | RSVD | |||
R/W-00b | R/W-0b | R/W-0b | R/W-1b | R/W-000b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7-6 | RSVD | R/W | 00b | Reserved. Should always be '00'. |
5 | STL_LRN | R/W | 0b | Write '1' to learn stall count for stall detection. This bit automatically returns to '0' when the stall learning process is complete. |
4 | EN_STL | R/W | 0b | 0b = Stall detection is disabled 1b = Stall detection is enabled |
3 | STL_REP | R/W | 1b | 0b = Stall detection is not reported on nFAULT 1b = Stall detection is reported on nFAULT |
2-1 | OL_TIME [1:0] | R/W | 00b | 00b = 200ms (max.) open load detection time 01b = 125ms (max.) open load detection time 10b = 75ms (max.) open load detection time 11b = 3ms (max.) open load detection time |
0 | EN_SR_BLANK | R/W | 0b | 0b = 500ns slow-decay to drive blanking time 1b = slow-decay to drive blanking will depend on slew rate, shown in Table 7-9. |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7-6 | RSVD | R/W | 00b | Reserved. Should always be '00'. |
5 | STL_LRN | R/W | 0b | Write '1' to learn stall count for stall detection. This bit automatically returns to '0' when the stall learning process is complete. |
4 | EN_STL | R/W | 0b | 0b = Stall detection is disabled 1b = Stall detection is enabled |
3 | STL_REP | R/W | 1b | 0b = Stall detection i s not reported on nFAULT 1b = Stall detection is reported on nFAULT |
2-0 | RSVD | R/W | 000b | Reserved. Should always be '000'. |
CTRL6 is shown in Figure 7-42 and described in Table 7-30.
Read/Write
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STALL_TH [7:0] | |||||||
R/W-00001111b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7-0 | STALL_TH [7:0] | R/W | 00001111b | 00000000b = 0 count XXXXXXXXb = 1 to 254 counts 11111111b = 255 counts |
CTRL7 is shown in Figure 7-43 and described in Table 7-31.
Read-only
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRQ_COUNT [7:0] | |||||||
R-11111111b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7-0 | TRQ_COUNT [7:0] | R | 11111111b | 00000000b = 0 count XXXXXXXXb = 1 to 254 counts 11111111b = 255 counts |
CTRL8 is shown in Figure 7-44 and described in Table 7-32.
Read-only
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | REV_ID [3:0] | ||||||
R-0000b | R-0010b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7-4 | RSVD | R | 0000b | Reserved |
3-0 | REV_ID | R | 0010b | Silicon Revision Identification. 0000b indicates 1st Prototype Revision. 0001b indicates 2nd Prototype Revision. 0010b indicates Production Revision. |