SNVSCF2 November   2025 LM65680

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Wettable Flanks
    2. 5.2 Pinout Design for Clearance and FMEA
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1  Input Voltage Range (VIN1, VIN2)
      2. 7.3.2  High-Voltage Bias Supply Subregulator (VCC, BIAS)
      3. 7.3.3  Precision Enable and Adjustable Input Voltage UVLO (EN/UVLO)
      4. 7.3.4  Output Voltage Setpoint (FB, BIAS)
      5. 7.3.5  Switching Frequency (RT)
      6. 7.3.6  Mode Selection and Clock Synchronization (MODE/SYNC)
        1. 7.3.6.1 Clock Synchronization
        2. 7.3.6.2 Clock Locking
      7. 7.3.7  Device Configuration (CNFG/SYNCOUT)
      8. 7.3.8  Dual-Random Spread Spectrum (DRSS)
      9. 7.3.9  High-Side MOSFET Gate Drive (BST)
      10. 7.3.10 Configurable Soft Start (SS)
        1. 7.3.10.1 Recovery From Dropout
      11. 7.3.11 Protection Features
        1. 7.3.11.1 Power-Good Monitor (PG)
        2. 7.3.11.2 Overcurrent and Short-Circuit Protection
        3. 7.3.11.3 Hiccup-Mode Protection
        4. 7.3.11.4 Thermal Shutdown
      12. 7.3.12 Two-Phase, Single-Output Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Train Components
        1. 8.1.1.1 Buck Inductor
        2. 8.1.1.2 Output Capacitors
        3. 8.1.1.3 Input Capacitors
        4. 8.1.1.4 EMI Filter
      2. 8.1.2 Error Amplifier and Compensation
      3. 8.1.3 Maximum Ambient Temperature
        1. 8.1.3.1 Derating Curves
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – 5V, 8A Synchronous Buck Regulator With Wide Input Voltage Range and High Efficiency
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Choosing the Switching Frequency
          3. 8.2.1.2.3  Buck Inductor Selection
          4. 8.2.1.2.4  Input Capacitor Selection
          5. 8.2.1.2.5  Output Capacitors
          6. 8.2.1.2.6  Output Voltage Setpoint
          7. 8.2.1.2.7  Compensation Components
          8. 8.2.1.2.8  Setting the Input Voltage UVLO
          9. 8.2.1.2.9  EMI Mitigation, RDRSS
          10. 8.2.1.2.10 Bootstrap Capacitor, CBST
        3. 8.2.1.3 Application Curves
      2.      Design 2 – High Efficiency, 48V to 12V, 400kHz Synchronous Buck Regulator
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Buck Inductor Selection
          2. 8.2.2.2.2 Input Capacitor Selection
          3. 8.2.2.2.3 Output Capacitors
          4. 8.2.2.2.4 Output Voltage Setpoint
          5. 8.2.2.2.5 Compensation Components
          6. 8.2.2.2.6 Feedforward Capacitor
          7. 8.2.2.2.7 Soft-Start Capacitor
        3. 8.2.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Thermal Design and Layout
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
        1. 9.2.1.1 Low-EMI Design Resources
        2. 9.2.1.2 Thermal Design Resources
        3. 9.2.1.3 Multiphase Design Resources
        4. 9.2.1.4 PCB Layout Resources
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 RZY 26-Pin WQFN-FCRLF Package (Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
NC 1 – No connect pin. Leave open.
PG 2 O Power-Good output pin. PG is an open-drain output that goes low if the output voltage is outside of the specified regulation window.
COMP 3 A External compensation pin. COMP is the output of the transconductance error amplifier. If used, connect a compensation network from COMP to PGND. If unused, tie COMP to PGND.
FB 4 A Feedback pin. Connect a resistor divider from VOUT to PGND to set the output voltage setpoint between 0.8V and 60V. Connect FB to VCC or PGND to configure 5V or 3.3V fixed output voltage, respectively. The FB regulation voltage is 0.8V.
SS 5 A Soft-start ramp programming pin. If SS is left open, the internal soft-start circuit ramps the FB reference from zero to full value in 5.3ms. Set the soft-start time to a higher value by connecting a capacitor from SS to PGND.
SGND 6 G System GND pin. Connect to the system ground.
CNFG/SYNCOUT 7 I/O Configuration pin. CNFG/SYNCOUT configures the device as a primary (single-phase or two-phase operation) or a secondary (two-phase operation) and selects internal (single-phase operation only) or external compensation (single-phase or two-phase operation). When configured as a primary for two-phase operation, the pin becomes a SYNCOUT pin after start-up.
MODE/SYNC 8 I Mode and synchronization input pin. Tie MODE/SYNC to PGND or drive low to operate in AUTO mode. Tie MODE/SYNC to VCC or drive high, or send a synchronization clock signal to operate in FPWM mode. When synchronized to an external clock, use RT to set the internal frequency close to the synchronized frequency to avoid disturbances if the external clock is turned on and off.
RT 9 A Switching frequency programming pin. Connect RT to PGND using a resistor with a value between 6.81kΩ and 54.2kΩ to set the switching frequency between 300kHz and 2.2MHz. Connect to VCC or PGND for fixed 400kHz or 2.2MHz operation, respectively. Do not leave RT open.
EN/UVLO 10 I Precision enable pin. Drive EN/UVLO high or low to enable or disable the device, respectively. EN/UVLO can directly connect to VIN. Use EN/UVLO with a resistor divider from VIN for adjustable input voltage UVLO. Do not leave EN/UVLO open.
NC 11 – No connect pin. Leave open.
PGND1 12 G Power ground to the internal low-side MOSFET. Connect this pin to the system ground. Provide a low-impedance connection to PGND2. Connect a high-quality bypass capacitor or capacitors from VIN1 to PGND1.
NC 13 – No connect pin. Leave open to maintain 1mm clearance between the VIN1 and PGND1 pins. Tying NC to PGND1 is possible provided that the 0.75mm clearance between VIN1 and PGND1 meets the system pin-clearance requirements.
VIN1 14 P Input supply to the regulator. Connect a high-quality bypass capacitor or capacitors from VIN1 to PGND1. Provide a low-impedance connection to VIN2.
NC 15 – No connect pin. Leave floating to maintain 0.5mm clearance between VIN1 and SW1.
SW1 16 P Device switch pins and the switch node of the regulator. Connect to the power-stage inductor.
SW2 17
SW3 18
BST 19 P High-side driver supply rail. Connect a 100nF capacitor between SW and BST. An internal diode charges the capacitor while SW is low.
NC 20 – No connect pin. Leave floating to maintain 0.5mm clearance between VIN2 and BST.
VIN2 21 P Input supply to the regulator. Connect a high-quality bypass capacitor or capacitors from VIN2 to PGND2. Provide a low-impedance connection to VIN1.
NC 22 – No connect pin. Leave open to maintain 1mm clearance between VIN2 and PGND2 pins. Tying NC to PGND2 is possible provided that the 0.75mm clearance between VIN2 and PGND2 pins meets the system pin-clearance requirements.
PGND2 23 G Power ground to the internal low-side MOSFET. Connect to system ground. Provide a low-impedance connection to PGND1. Connect a high-quality bypass capacitor or capacitors from VIN2 to PGND2.
VCC 24 P Internal regulator output. Used as a supply to the internal control circuits. Connect a high-quality 1µF capacitor from VCC to PGND. Do not connect VCC to any external loads.
DRSS/MCOMM 25 I/O Dual Random Spread Spectrum (DRSS) select pin. See Dual-Random Spread Spectrum (DRSS) for available DRSS options. When configured for two-phase operation, DRSS/MCOMM becomes a mode communication pin between the primary and secondary devices. Connect the DRSS/MCOMM pins of the primary and secondary.
BIAS 26 P Input to an internal voltage regulator. For fixed output configurations of 3.3V or 5V, connect BIAS to the VOUT node for output voltage sensing. For adjustable output configurations, connect BIAS to the VOUT node or to an external bias supply from 3.3V to 30V. If the output voltage is above 30V and an external bias supply is not available, tie BIAS to PGND.
PGND – G Exposed PGND pad. Connect to system GND on the PCB. This pad is a major heat dissipation path for the device. Use the pad for heatsinking by soldering to a large copper area on the PCB. Implement as many thermal vias as suggested in the example board layout to reduce package thermal resistance and improve thermal performance.
(1) P = Power, G = Ground, A = Analog, I = Input, O = Output.