SNVSAL1C December 2017 – June 2021 LP87702-Q1
The LP87702-Q1 device monitors the input voltage from the VANA pin in the standby and active operation modes. If the input voltage rises above the VANAOVP voltage level, all the converters are disabled immediately (without switching ramp or shutdown delays), the pulldown resistors discharge the output voltages (BUCKx_RDIS_EN = 1 and BOOST_RDIS_EN = 1), the GPOs are set to the logic low level, the nINT signal is pulled low, the OVP_INT bit is set to 1, and BUCKx_STAT and BOOST_STAT bits are set to 0. The host processor clears the interrupt by writing 1 to the OVP_INT bit. If the input voltage is above over-voltage detection level, the interrupt is not cleared. The host can read the status of the overvoltage from the OVP_STAT bit. Converters cannot be enabled as long as the input voltage is above over-voltage detection level or the overvoltage interrupt is pending.