SNVSAL1C December 2017 – June 2021 LP87702-Q1
In this mode the PGx signal shows the validity of the requested voltages continuously. Mode is selected by setting the PGx_MODE bit to 1 in the PG_CTRL register.
For the continuous mode of operation, the PGx behaves as follows:
When an invalid output voltage of monitored converter is detected, the corresponding bit in the PG0_FAULT or PG1_FAULT register is set to 1 and the PGx signal becomes inactive. The PG0_FAULT and PG1_FAULT register bits are latched and maintain the fault information until host clears the fault bit by writing 1 to the bit. The PGx signal also indicates the interrupts from VANA, VMON1, and VMON2 inputs and thermal warning and shutdown. All are cleared by clearing the interrupt bits.
The PGx signal is set inactive when the converter voltage is transitioning from one target voltage to another.
The source for the fault can be read from PGx_FAULT register when PGx signal becomes inactive. If the invalid output voltage becomes valid again the PGx signal becomes active. Thus the PGx signal shows all the time if the monitored output voltages are valid. Figure 8-11 shows an example of the PGx pin operation in continuous mode.
The PGx signal can also be configured so that it maintains the inactive state even when the monitored outputs are valid, but there are PG_FAULT_x bits pending clearance. This type of operation is selected by setting the PGOOD_FAULT_GATES_PGx bit to 1.