SNVSAL1C December 2017 – June 2021 LP87702-Q1
The PGx signal detects unexpected or unusual situations in this mode. Mode is selected by setting the PGx_MODE bit to 0 in the PG_CTRL register.
For the gated mode of operation, the PGx behaves as follows:
PGx signal is set inactive if the output voltage of a monitored buck or boost converter is invalid or the output voltage is not valid at 800 µs from the enable of the converter, which should be considered when selecting the BUCKx_SLEW_RATE setting. Keep the sum of the soft start time and slew rate controlled part of the voltage ramp below 800 µs to avoid PGx triggering at start-up. In addition, the PGx is inactive when the invalid input voltage at VANA, VMON1, or VMON2 pin is detected.
Detected fault sets the corresponding fault bit in PG0_FAULT or in PG1_FAULT register. The detected fault must be cleared to continue the PGx monitoring. The over-voltage and thermal faults are cleared by writing 1 to the corresponding interrupt bits in INT_TOP_1 register. Converter, VMONx and VANA faults are cleared by writing 1 to the corresponding register bit in INT_BUCK, INT_BOOST, and INT_DIAG register, respectively. An example of the PGx pin operation in gated mode is shown in Figure 8-10 and the different use cases for the PGx signal operation are summarized in Table 8-6.