SNVSAL1C December 2017 – June 2021 LP87702-Q1
The LP87702-Q1 device contains a CLKIN input to synchronize buck and boost converters' switching clock with the external clock. Figure 8-3 shows the block diagram of the clocking and PLL module. Table 8-2 shows how the external clock is selected and interrupt is generated depending on the EN_PLL bit in PLL_CTRL register and the external clock availability. The interrupt can be masked with SYNC_CLK_MASK bit in TOP_MASK_1 register. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[4:0] bits in PLL_CTRL register and it can be from 1 MHz to 24 MHz with 1-MHz steps. The external clock must be inside accuracy limits (–30%/+10%) for valid clock detection.
The SYNC_CLK_INT interrupt in INT_TOP_1 register is also generated in cases the external clock is expected but it is not available. These cases are Startup (Read OTP-to-standby transition) when EN_PLL = 1 and buck or boost converter is enabled (standby-to-active transition) when EN_PLL = 1.
|DEVICE OPERATION MODE||EN_PLL||PLL AND CLOCK DETECTOR STATE||INTERRUPT FOR EXTERNAL CLOCK||CLOCK|
|STANDBY||1||Enabled||When external clock disappears or appears||Automatic change to internal RC oscillator when External clock is not available|
|ACTIVE||1||Enabled||When external clock disappears or appears||Automatic change to internal RC oscillator when External clock is not available|