The power-up sequence for the LP87702-Q1 is as follows:
- VANA (and VIN_Bx) reach minimum recommended levels (VVANA > VANAUVLO).
- Driving the NRST input high initiates OTP read and enables the system I/O
interface. Minimum delay from the NRST reset input
rising edge to I2C write or read access is 1.2
- Device enters STANDBY mode. Watchdog operation starts.
- The host can change the default register setting by I2C if needed.
- The converters can be enabled or disabled and the
GPOx signals can be controlled by ENx pins and by