SNVSAL1C December   2017  – June 2021 LP87702-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Parameters
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Descriptions
      1. 8.3.1  Step-Down DC/DC Converters
        1. Overview
        2. Transition Between PWM and PFM Modes
        3. Buck Converter Load Current Measurement
      2. 8.3.2  Boost Converter
      3. 8.3.3  Spread-Spectrum Mode
      4. 8.3.4  Sync Clock Functionality
      5. 8.3.5  Power-Up
      6. 8.3.6  Buck and Boost Control
        1. Enabling and Disabling Converters
        2. Changing Buck Output Voltage
      7. 8.3.7  Enable and Disable Sequences
      8. 8.3.8  Window Watchdog
      9. 8.3.9  Device Reset Scenarios
      10. 8.3.10 Diagnostics and Protection Features
        1. Voltage Monitorings
        2. Interrupts
        3. Power-Good Information to Interrupt, PG0, and PG1 Pins
          1. PGx Pin Gated (Unusual) Mode
          2. PGx Pin Operation in Continuous Mode
          3. Summary of PG0, PG1 Gated, and Continuous Operating Modes
        4. Warning Interrupts for System Level Diagnostics
          1. Output Power Limit
          2. Thermal Warning
        5. Protections Causing Converter Disable
          1. Short-Circuit and Overload Protection
          2. Overvoltage Protection
          3. Thermal Shutdown
        6. Protections Causing Device Power Down
          1. Undervoltage Lockout
      11. 8.3.11 OTP Error Correction
      12. 8.3.12 Operation of GPO Signals
      13. 8.3.13 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. Data Validity
        2. Start and Stop Conditions
        3. Transferring Data
        4. I2C-Compatible Chip Address
        5. Auto Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. LP8770_map Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Application Components
          1. Inductor Selection
          2. Buck Input Capacitor Selection
          3. Buck Output Capacitor Selection
          4. Boost Input Capacitor Selection
          5. Boost Output Capacitor Selection
          6. Supply Filtering Components
      3. 9.2.3 Current Limit vs Maximum Output Current
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power-Good Information to Interrupt, PG0, and PG1 Pins

LP87702-Q1 supports both interrupt based indication of the power-good levels for various voltage settings and uses two power-good signals, PG0 and PG1. The selection of monitored signals is independent for the interrupt (nINT) and PG0 and PG1 signals. Each signal can include the following:

  • The output voltage of one or both BUCKx converters
  • The output voltage of the BOOST converter
  • Input voltage of VANA
  • Input voltage of VMON1 and VMON2 or both
  • Thermal warning

Figure 8-9 shows the block diagram for power-good connections to PG0 and PG1 pins and interrupt.

Monitored signals are enabled in the PGOOD_CTRL register. Converter output voltage monitoring (not current limit monitoring) can be selected for the indication. Monitoring is enabled by the EN_PGOOD_BUCKx and EN_PGOOD_BOOST bits. The monitoring is automatically masked to prevent it from forcing PGx inactive or causing an interrupt when a converter is disabled. Also, monitoring of VANA, VMON1, and VMON2 inputs can be independently enabled through the PGOOD_CTRL register. The type of voltage monitoring for the PGx signals and nINT is selected by the PGOOD_WINDOW bit. Only the undervoltage is monitored if the bit is 0 and the undervoltage and overvoltage are monitored if the bit is 1. See Section for voltage monitoring thresholds.

Monitoring interrupts from all the output rails, input rails, and thermal warning are combined to the nINT pin. Dedicated mask bits are used to select which interrupts control the state of the nINT pin. See Table 8-5 for summary of the interrupts, mask bits, and interrupt clearing.

Similarly, enabled monitoring signals from all the output rails, input rails, and thermal warning are combined to PG0 and PG1 output pins. Register bits (SEL_PGx_x in PG0_CTRL and PG1_CTRL) select which of the signals control the state of PG0 and PG1, respectively. The polarity and the output type (push-pull or open-drain) of PG0 and PG1 are selected by the PGx_POL and PGx_OD bits in the PG_CTRL register.

PGx is only active or asserted when all monitored input voltages and all output voltages of the monitored and enabled converters are within the specified tolerance of the set target value.

PGx is inactive or de-asserted if any of the monitored input voltages or output voltages of the monitored and enabled converters are outside the specified tolerance of the set target value.

When PGx_RISE_DELAY = 1, PGx is set as active or asserted with 11 ms delay from the point of time where all the enabled power resource output voltages are within the specified tolerance for each requested or programmed output voltage.

Thermal shutdown and VANA overvoltage protection events force the PGx to the default state (the PGx are driven low, assuming the PGx polarity set in the OTP is active high).

GUID-C6CF046C-F76A-457B-BB31-18BDA0D065BA-low.gif Figure 8-9 Block Diagram of Power-Good Connections

LP87702-Q1 power-good detection has two operating modes selected in the OTP: gated (that is, unusual) or continuous (that is, invalid) mode of operation. These modes are described in Section and in Section