SNVSAL1C December   2017  – June 2021 LP87702-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Parameters
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Descriptions
      1. 8.3.1  Step-Down DC/DC Converters
        1. 8.3.1.1 Overview
        2. 8.3.1.2 Transition Between PWM and PFM Modes
        3. 8.3.1.3 Buck Converter Load Current Measurement
      2. 8.3.2  Boost Converter
      3. 8.3.3  Spread-Spectrum Mode
      4. 8.3.4  Sync Clock Functionality
      5. 8.3.5  Power-Up
      6. 8.3.6  Buck and Boost Control
        1. 8.3.6.1 Enabling and Disabling Converters
        2. 8.3.6.2 Changing Buck Output Voltage
      7. 8.3.7  Enable and Disable Sequences
      8. 8.3.8  Window Watchdog
      9. 8.3.9  Device Reset Scenarios
      10. 8.3.10 Diagnostics and Protection Features
        1. 8.3.10.1 Voltage Monitorings
        2. 8.3.10.2 Interrupts
        3. 8.3.10.3 Power-Good Information to Interrupt, PG0, and PG1 Pins
          1. 8.3.10.3.1 PGx Pin Gated (Unusual) Mode
          2. 8.3.10.3.2 PGx Pin Operation in Continuous Mode
          3. 8.3.10.3.3 Summary of PG0, PG1 Gated, and Continuous Operating Modes
        4. 8.3.10.4 Warning Interrupts for System Level Diagnostics
          1. 8.3.10.4.1 Output Power Limit
          2. 8.3.10.4.2 Thermal Warning
        5. 8.3.10.5 Protections Causing Converter Disable
          1. 8.3.10.5.1 Short-Circuit and Overload Protection
          2. 8.3.10.5.2 Overvoltage Protection
          3. 8.3.10.5.3 Thermal Shutdown
        6. 8.3.10.6 Protections Causing Device Power Down
          1. 8.3.10.6.1 Undervoltage Lockout
      11. 8.3.11 OTP Error Correction
      12. 8.3.12 Operation of GPO Signals
      13. 8.3.13 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C-Compatible Chip Address
        5. 8.5.1.5 Auto Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1 LP8770_map Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application Components
          1. 9.2.2.1.1 Inductor Selection
          2. 9.2.2.1.2 Buck Input Capacitor Selection
          3. 9.2.2.1.3 Buck Output Capacitor Selection
          4. 9.2.2.1.4 Boost Input Capacitor Selection
          5. 9.2.2.1.5 Boost Output Capacitor Selection
          6. 9.2.2.1.6 Supply Filtering Components
      3. 9.2.3 Current Limit vs Maximum Output Current
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.6.1 Enabling and Disabling Converters

The buck converters can be enabled when the device is in STANDBY or ACTIVE state. There are two ways to enable and disable the buck converters:

  • Using BUCKx_EN bit in BUCKx_CTRL_1 register (BUCKx_EN_PIN_CTRL bit is 00 in BUCKx_CTRL_1 register)
  • Using ENx control pin (BUCKx_EN bit is 1 in BUCKx_CTRL_1 register and BUCKx_EN_PIN_CTRL bit is not 00 in BUCKx_CTRL_1 register)

Similarly there are two ways to enable and disable the boost converter:

  • Using BOOST_EN bit in BOOST_CTRL register (BOOST_EN_PIN_CTRL bit is 0 in BOOST_CTRL register)
  • Using ENx control pin (BOOST_EN bit is 1 in BOOST_CTRL register and BOOST_EN_PIN_CTRL bit is not 00 in BOOST_CTRL register)

If the ENx control pin is used to enable and disable, then the delay from the control signal rising edge to start-up is set by BUCKx_STARTUP_DELAY[3:0] bits in BUCKx_DELAY register and BOOST_STARTUP_DELAY[3:0] bits in BOOST_DELAY register. The delay from falling edge of control signal to shutdown is set by BUCKx_SHUTDOWN_DELAY[3:0] bits in BUCKx_DELAY register and BOOST_SHUTDOWN_DELAY[3:0] bits in BOOST_DELAY register. The delays are valid only when ENx pin control is used, not when converters are enabled by I2C write to BUCKx_EN and BOOST_EN bits.

The control of the converters (with 0-ms delays) is shown in Table 8-3.

Table 8-3 Converter Control
BUCKx_EN /
BOOST_EN		BUCKx_EN_PIN_CTRL /
BOOST_EN_PIN_CTRL		EN1 PINEN2 PINEN3 PINBUCKx OUTPUT VOLTAGE /
BOOST OUTPUT VOLTAGE
Enable or disable control with BUCKx_EN/BOOST_EN bit0Don't CareDon't CareDon't CareDon't CareDisabled
100Don't CareDon't CareDon't CareBUCKx_VSET[7:0] / BOOST_VSET[1:0]
Enable or disable control with EN1 pin101LowDon't CareDon't CareDisabled
101HighDon't CareDon't CareBUCKx_VSET[7:0] / BOOST_VSET[1:0]
Enable/disable control with EN2 pin110Don't CareLowDon't CareDisabled
110Don't CareHighDon't CareBUCKx_VSET[7:0] / BOOST_VSET[1:0]
Enable or disable control with EN3 pin111Don't CareDon't CareLowDisabled
111Don't CareDon't CareHighBUCKx_VSET[7:0] / BOOST_VSET[1:0]

Figure 8-4 shows how the BUCKx converter is enabled by an ENx pin or by I2C write access. The soft-start circuit limits the in-rush current during start-up. The output voltage increase rate is typically 30 mV/μsec during soft start. The output voltage becomes slew-rate controlled when the output voltage rises to 0.35-V level. If there is a short circuit at the output and the output voltage does not increase above a 0.35-V level in 1 ms, the converter is disabled, and interrupt is set. When the output voltage rises above the undervoltage power-good threshold level the BUCKx_PG_INT interrupt flag in the INT_BUCK register is set.

Power-good thresholds are defined by BUCKx_WINDOW bits. A PGOOD_WINDOW bit in PGOOD_CTRL register sets the detection method for the valid buck output voltage, either undervoltage detection or undervoltage and overvoltage detection. The powergood interrupt flag can be masked using the BUCKx_PGR_MASK bit in the BUCK_MASK register when reaching the valid output voltage. The power-good interrupt flag can also be generated when the output voltage becomes invalid. The interrupt mask for invalid output voltage detection is set by BUCKx_PGF_MASK bit in BUCK_MASK register. When the window monitoring (under and overvoltage monitoring) is selected, the mask bits apply when voltage is crossing either threshold. A BUCKx_PG_STAT bit in BUCK_STAT register shows always the validity of the output voltage; '1' means valid, and '0' means invalid output voltage.

GUID-06678DE9-E7AE-40B5-873C-FF549DA5FF02-low.gifFigure 8-4 Buck Converter Enable and Disable

Figure 8-5 shows how the boost converter is enabled by an ENx pin or by I2C write access. The soft-start circuit limits the in-rush current during start-up. The output voltage increase rate is less than 100 mV/μsec during soft start. If there is a short circuit at the output and the output voltage does not reach the input voltage level in 1 ms, the converter is disabled, and the interrupt is set. When the output voltage reaches the power-good threshold level, the BOOST_PG_INT interrupt flag in INT_BOOST register is set.

Power-good thresholds are defined by BOOST_WINDOW bits. A PGOOD_WINDOW bit in PGOOD_CTRL register sets the detection method for the valid boost output voltage, either undervoltage detection or undervoltage and overvoltage detection. The power-good interrupt flag, when reaching valid output voltage, can be masked using BOOST_PGR_MASK bit in BOOST_MASK register. The power-good interrupt flag can also be generated when the output voltage becomes invalid. The interrupt mask for invalid output voltage detection is set by the BOOST_PGF_MASK bit in BOOST_MASK register. A BOOST_PG_STAT bit in the BOOST_STAT register always shows the validity of the output voltage; '1' means valid and '0' means invalid output voltage.

The ENx input pins have integrated pulldown resistors. The pulldown resistors are enabled by default and host can disable those with ENx_PD bits in CONFIG register.

GUID-256E5E1B-C057-4CD0-A908-0BCAC1671986-low.gifFigure 8-5 Boost Converter Enable and Disable