SNVSAL1C December 2017 – June 2021 LP87702-Q1
The buck and boost converters are disabled immediately (without switching ramp or without any shutdown delays), and the output capacitor is discharged using the pulldown resistor, and the LP87702-Q1 device enters SHUTDOWN when the input voltage falls below VANAUVLO at the VANA pin. The device powers up to STANDBY state when the V(VANA) voltage is above the VANAUVLO threshold level.
If the reset interrupt is unmasked by default (RESET_REG_MASK = 0 in TOP_MASK_2 register), the RESET_REG_INT interrupt in the INT_TOP_2 register indicates that the device has been in SHUTDOWN. The host processor must clear the interrupt by writing 1 to the RESET_REG_INT bit. If the host processor reads the RESET_REG_INT flag after detecting an nINT low signal, it detects that the input supply voltage has been below the VANAUVLO level (or the host has requested reset with the RESET(SW_RESET) bit), and the registers are reset to the default values.